# Timing Messages

Report Title | Timing Analysis Report
Design File | Z:\hdmi\impl\gwsynthesis\hdmi.vg
Physical Constraints File | Z:\hdmi\src\hdmi.cst
Timing Constraint File | Z:\hdmi\src\hdmi.sdc
Tool Version | V1.9.12 (64-bit)
Part Number | GW1NR-LV9QN88PC6/I5
Device | GW1NR-9
Device Version | C
Created Time | Wed Apr 1 21:06:43 2026
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

# Timing Summaries

## STA Tool Run Summary:

Setup Delay Model | Slow 1.14V 85C C6/I5
Hold Delay Model | Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed | 7516
Numbers of Endpoints Analyzed | 3556
Numbers of Falling Endpoints | 568
Numbers of Setup Violated Endpoints | 27
Numbers of Hold Violated Endpoints | 0

## Clock Summary:

NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects
--- | --- | --- | --- | --- | --- | --- | --- | --- | ---
1 | clk_osc | Base | 37.037 | 27.000 | 0.000 | 18.518 |  |  | clk
2 | cpuclk | Base | 20.000 | 50.000 | 0.000 | 10.000 |  |  | cpuclk_ibuf/I
3 | test1/wng1/fsr_clk | Base | 20.000 | 50.000 | 0.000 | 10.000 |  |  | test1/wng1/fsr_clk_s0/Q
4 | svo_hdmi_inst/svo_tcard/bram_aclock | Base | 20.000 | 50.000 | 0.000 | 10.000 |  |  | svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
5 | u_pll/rpll_inst/CLKOUT.default_gen_clk | Generated | 7.936 | 126.000 | 0.000 | 3.968 | clk_ibuf/I | clk_osc | u_pll/rpll_inst/CLKOUT
6 | u_pll/rpll_inst/CLKOUTP.default_gen_clk | Generated | 7.936 | 126.000 | 0.000 | 3.968 | clk_ibuf/I | clk_osc | u_pll/rpll_inst/CLKOUTP
7 | u_pll/rpll_inst/CLKOUTD.default_gen_clk | Generated | 15.873 | 63.000 | 0.000 | 7.936 | clk_ibuf/I | clk_osc | u_pll/rpll_inst/CLKOUTD
8 | u_pll/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 23.809 | 42.000 | 0.000 | 11.905 | clk_ibuf/I | clk_osc | u_pll/rpll_inst/CLKOUTD3
9 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | Generated | 39.682 | 25.200 | 0.000 | 19.841 | u_pll/rpll_inst/CLKOUT | u_pll/rpll_inst/CLKOUT.default_gen_clk | u_div_5/clkdiv_inst/CLKOUT

## Max Frequency Summary:

NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity
--- | --- | --- | --- | --- | ---
1 | cpuclk | 50.000(MHz) | 29.060(MHz) | 23 | TOP
2 | test1/wng1/fsr_clk | 50.000(MHz) | 420.901(MHz) | 2 | TOP
3 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | 25.200(MHz) | 24.154(MHz) | 11 | TOP

#### No timing paths to get frequency of clk_osc!

#### No timing paths to get frequency of svo_hdmi_inst/svo_tcard/bram_aclock!

#### No timing paths to get frequency of u_pll/rpll_inst/CLKOUT.default_gen_clk!

#### No timing paths to get frequency of u_pll/rpll_inst/CLKOUTP.default_gen_clk!

#### No timing paths to get frequency of u_pll/rpll_inst/CLKOUTD.default_gen_clk!

#### No timing paths to get frequency of u_pll/rpll_inst/CLKOUTD3.default_gen_clk!

## Total Negative Slack Summary:

Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints
--- | --- | --- | ---
clk_osc | Setup | 0.000 | 0
clk_osc | Hold | 0.000 | 0
cpuclk | Setup | -81.887 | 7
cpuclk | Hold | 0.000 | 0
test1/wng1/fsr_clk | Setup | 0.000 | 0
test1/wng1/fsr_clk | Hold | 0.000 | 0
svo_hdmi_inst/svo_tcard/bram_aclock | Setup | 0.000 | 0
svo_hdmi_inst/svo_tcard/bram_aclock | Hold | 0.000 | 0
u_pll/rpll_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0
u_pll/rpll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0
u_pll/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0
u_pll/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0
u_pll/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0
u_pll/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0
u_pll/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0
u_pll/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0
u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | Setup | -1.253 | 2
u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0

# Timing Details

## Path Slacks Table:

### Setup Paths Table

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | -14.411 | test1/wng1/noiseact_s0/Q | test1/dac1/outshr_10_s0/D | cpuclk:[R] | cpuclk:[R] | 20.000 | 0.000 | 34.011
2 | -14.218 | test1/env1/env_amp_2_s0/Q | test1/dac1/outshr_11_s0/D | cpuclk:[R] | cpuclk:[R] | 20.000 | 0.000 | 33.818
3 | -14.175 | test1/wng1/noiseact_s0/Q | test1/dac1/outshr_9_s0/D | cpuclk:[R] | cpuclk:[R] | 20.000 | 0.000 | 33.775
4 | -11.987 | test1/wng1/noiseact_s0/Q | test1/dac1/outshr_8_s0/D | cpuclk:[R] | cpuclk:[R] | 20.000 | 0.000 | 31.587
5 | -11.480 | test1/wng1/noiseact_s0/Q | test1/dac1/outshr_7_s0/D | cpuclk:[R] | cpuclk:[R] | 20.000 | 0.000 | 31.080
6 | -10.080 | test1/wng1/noiseact_s0/Q | test1/dac1/outshr_6_s0/D | cpuclk:[R] | cpuclk:[R] | 20.000 | 0.000 | 29.680
7 | -5.536 | test1/env1/env_amp_0_s0/Q | test1/dac1/outshr_5_s0/D | cpuclk:[R] | cpuclk:[R] | 20.000 | 0.000 | 25.136
8 | -2.720 | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12/CEA | cpuclk:[F] | svo_hdmi_inst/svo_tcard/bram_aclock:[R] | 10.000 | 2.499 | 10.017
9 | -0.859 | svo_hdmi_inst/svo_tcard/txtmode0/hpixelcount_7_s0/Q | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12/CEB | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | 19.841 | 0.015 | 20.498
10 | -1.151 | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_4/CEA | cpuclk:[F] | svo_hdmi_inst/svo_tcard/bram_aclock:[R] | 10.000 | 2.499 | 8.448
11 | -0.965 | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_18/CEA | cpuclk:[F] | svo_hdmi_inst/svo_tcard/bram_aclock:[R] | 10.000 | 2.499 | 8.262
12 | -0.812 | svo_hdmi_inst/svo_tcard/bramwraddr_9_s0/Q | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16/ADA[11] | cpuclk:[F] | svo_hdmi_inst/svo_tcard/bram_aclock:[R] | 10.000 | 2.499 | 8.239
13 | -0.394 | svo_hdmi_inst/svo_tcard/grmode1/memcounth_5_s0/Q | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_18/CEB | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | 19.841 | 0.015 | 20.034
14 | -0.727 | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_17/CEA | cpuclk:[F] | svo_hdmi_inst/svo_tcard/bram_aclock:[R] | 10.000 | 2.499 | 8.024
15 | -0.664 | svo_hdmi_inst/svo_tcard/bramwraddr_9_s0/Q | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_8/ADA[11] | cpuclk:[F] | svo_hdmi_inst/svo_tcard/bram_aclock:[R] | 10.000 | 2.499 | 8.091
16 | -0.654 | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16/CEA | cpuclk:[F] | svo_hdmi_inst/svo_tcard/bram_aclock:[R] | 10.000 | 2.499 | 7.951
17 | -0.621 | svo_hdmi_inst/svo_tcard/bramwraddr_12_s0/Q | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_15/CEA | cpuclk:[F] | svo_hdmi_inst/svo_tcard/bram_aclock:[R] | 10.000 | 2.499 | 7.918
18 | -0.569 | svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/Q | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_11/CEA | cpuclk:[F] | svo_hdmi_inst/svo_tcard/bram_aclock:[R] | 10.000 | 2.499 | 7.866
19 | -0.560 | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_8/CEA | cpuclk:[F] | svo_hdmi_inst/svo_tcard/bram_aclock:[R] | 10.000 | 2.499 | 7.857
20 | -0.497 | svo_hdmi_inst/svo_tcard/bramwraddr_9_s0/Q | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12/ADA[11] | cpuclk:[F] | svo_hdmi_inst/svo_tcard/bram_aclock:[R] | 10.000 | 2.499 | 7.925
21 | -0.283 | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_0/CEA | cpuclk:[F] | svo_hdmi_inst/svo_tcard/bram_aclock:[R] | 10.000 | 2.499 | 7.580
22 | -0.261 | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_9/CEA | cpuclk:[F] | svo_hdmi_inst/svo_tcard/bram_aclock:[R] | 10.000 | 2.499 | 7.558
23 | -0.215 | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_14/CEA | cpuclk:[F] | svo_hdmi_inst/svo_tcard/bram_aclock:[R] | 10.000 | 2.499 | 7.512
24 | -0.209 | svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/Q | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_3/CEA | cpuclk:[F] | svo_hdmi_inst/svo_tcard/bram_aclock:[R] | 10.000 | 2.499 | 7.506
25 | -0.192 | svo_hdmi_inst/svo_tcard/bramwraddr_0_s0/Q | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16/ADA[2] | cpuclk:[F] | svo_hdmi_inst/svo_tcard/bram_aclock:[R] | 10.000 | 2.499 | 7.620

### Hold Paths Table

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.052 | test1/wng1/lfsr1/sfr_1_s0/Q | test1/wng1/noiseout_s0/D | test1/wng1/fsr_clk:[R] | cpuclk:[R] | 0.000 | -1.444 | 1.525
2 | 0.555 | svo_hdmi_inst/svo_tmds_1/dout_9_s0/Q | svo_hdmi_inst/tmds_serdes[1]/D9 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.568
3 | 0.555 | svo_hdmi_inst/svo_tmds_1/dout_9_s0/Q | svo_hdmi_inst/tmds_serdes[1]/D2 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.568
4 | 0.559 | svo_hdmi_inst/svo_tmds_2/dout_3_s0/Q | svo_hdmi_inst/tmds_serdes[2]/D3 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.572
5 | 0.559 | svo_hdmi_inst/svo_tmds_2/dout_3_s0/Q | svo_hdmi_inst/tmds_serdes[2]/D1 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.572
6 | 0.708 | svo_hdmi_inst/svo_tcard/grmode1/prescnibble_0_s1/Q | svo_hdmi_inst/svo_tcard/grmode1/prescnibble_0_s1/D | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | 0.000 | 0.000 | 0.708
7 | 0.708 | svo_hdmi_inst/svo_tcard/grmode1/prescnibble_1_s0/Q | svo_hdmi_inst/svo_tcard/grmode1/prescnibble_1_s0/D | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | 0.000 | 0.000 | 0.708
8 | 0.708 | svo_hdmi_inst/svo_tcard/grmode1/prescl_1_s0/Q | svo_hdmi_inst/svo_tcard/grmode1/prescl_1_s0/D | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | 0.000 | 0.000 | 0.708
9 | 0.708 | svo_hdmi_inst/svo_tcard/grmode1/memcountl_4_s0/Q | svo_hdmi_inst/svo_tcard/grmode1/memcountl_4_s0/D | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | 0.000 | 0.000 | 0.708
10 | 0.708 | svo_hdmi_inst/svo_tcard/grmode1/memcounth_5_s0/Q | svo_hdmi_inst/svo_tcard/grmode1/memcounth_5_s0/D | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | 0.000 | 0.000 | 0.708
11 | 0.708 | svo_hdmi_inst/svo_tcard/txtmode0/memlinebase_8_s0/Q | svo_hdmi_inst/svo_tcard/txtmode0/memlinebase_8_s0/D | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | 0.000 | 0.000 | 0.708
12 | 0.708 | svo_hdmi_inst/svo_tcard/pixelcount_1_s1/Q | svo_hdmi_inst/svo_tcard/pixelcount_1_s1/D | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | 0.000 | 0.000 | 0.708
13 | 0.708 | svo_hdmi_inst/svo_tcard/pixelcount_8_s0/Q | svo_hdmi_inst/svo_tcard/pixelcount_8_s0/D | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | 0.000 | 0.000 | 0.708
14 | 0.708 | svo_hdmi_inst/svo_tcard/pixelcount_14_s0/Q | svo_hdmi_inst/svo_tcard/pixelcount_14_s0/D | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F] | 0.000 | 0.000 | 0.708
15 | 0.708 | svo_hdmi_inst/svo_tcard/cled3_0_s3/Q | svo_hdmi_inst/svo_tcard/cled3_0_s3/D | cpuclk:[F] | cpuclk:[F] | 0.000 | 0.000 | 0.708
16 | 0.708 | svo_hdmi_inst/svo_tcard/bramwraddr_6_s0/Q | svo_hdmi_inst/svo_tcard/bramwraddr_6_s0/D | cpuclk:[F] | cpuclk:[F] | 0.000 | 0.000 | 0.708
17 | 0.708 | svo_hdmi_inst/svo_tcard/counter_0_s0/Q | svo_hdmi_inst/svo_tcard/counter_0_s0/D | cpuclk:[F] | cpuclk:[F] | 0.000 | 0.000 | 0.708
18 | 0.708 | ps2_1/bitsreceived_2_s0/Q | ps2_1/bitsreceived_2_s0/D | cpuclk:[R] | cpuclk:[R] | 0.000 | 0.000 | 0.708
19 | 0.708 | ps2_1/bitsreceived_3_s0/Q | ps2_1/bitsreceived_3_s0/D | cpuclk:[R] | cpuclk:[R] | 0.000 | 0.000 | 0.708
20 | 0.708 | test1/dac1/state_4_s0/Q | test1/dac1/state_4_s0/D | cpuclk:[R] | cpuclk:[R] | 0.000 | 0.000 | 0.708
21 | 0.708 | test1/wng1/clkdiv_1_s2/Q | test1/wng1/clkdiv_1_s2/D | cpuclk:[R] | cpuclk:[R] | 0.000 | 0.000 | 0.708
22 | 0.708 | test1/wng1/clkdiv_2_s0/Q | test1/wng1/clkdiv_2_s0/D | cpuclk:[R] | cpuclk:[R] | 0.000 | 0.000 | 0.708
23 | 0.708 | test1/wng1/clkdiv_4_s0/Q | test1/wng1/clkdiv_4_s0/D | cpuclk:[R] | cpuclk:[R] | 0.000 | 0.000 | 0.708
24 | 0.708 | test1/wng1/clkdiv_5_s0/Q | test1/wng1/clkdiv_5_s0/D | cpuclk:[R] | cpuclk:[R] | 0.000 | 0.000 | 0.708
25 | 0.708 | test1/toneC/clkdiv_3_s0/Q | test1/toneC/clkdiv_3_s0/D | cpuclk:[R] | cpuclk:[R] | 0.000 | 0.000 | 0.708

### Recovery Paths Table

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 1.370 | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q | svo_hdmi_inst/tmds_serdes[0]/RESET | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_pll/rpll_inst/CLKOUT.default_gen_clk:[F] | 3.968 | -1.943 | 4.466
2 | 1.370 | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q | svo_hdmi_inst/tmds_serdes[1]/RESET | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_pll/rpll_inst/CLKOUT.default_gen_clk:[F] | 3.968 | -1.943 | 4.466
3 | 1.370 | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q | svo_hdmi_inst/tmds_serdes[2]/RESET | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_pll/rpll_inst/CLKOUT.default_gen_clk:[F] | 3.968 | -1.943 | 4.466
4 | 5.332 | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q | svo_hdmi_inst/tmds_serdes[2]/RESET | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_pll/rpll_inst/CLKOUT.default_gen_clk:[R] | 7.936 | -1.937 | 4.466
5 | 5.332 | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q | svo_hdmi_inst/tmds_serdes[1]/RESET | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_pll/rpll_inst/CLKOUT.default_gen_clk:[R] | 7.936 | -1.937 | 4.466
6 | 5.332 | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q | svo_hdmi_inst/tmds_serdes[0]/RESET | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_pll/rpll_inst/CLKOUT.default_gen_clk:[R] | 7.936 | -1.937 | 4.466
7 | 35.171 | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q | svo_hdmi_inst/tmds_serdes[2]/RESET | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | 39.682 | 0.000 | 4.466
8 | 35.171 | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q | svo_hdmi_inst/tmds_serdes[1]/RESET | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | 39.682 | 0.000 | 4.466
9 | 35.171 | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q | svo_hdmi_inst/tmds_serdes[0]/RESET | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | 39.682 | 0.000 | 4.466

### Removal Paths Table

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.812 | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q | svo_hdmi_inst/tmds_serdes[0]/RESET | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_pll/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | -1.965 | 2.820
2 | 0.812 | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q | svo_hdmi_inst/tmds_serdes[1]/RESET | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_pll/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | -1.965 | 2.820
3 | 0.812 | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q | svo_hdmi_inst/tmds_serdes[2]/RESET | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_pll/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | -1.965 | 2.820
4 | 2.807 | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q | svo_hdmi_inst/tmds_serdes[2]/RESET | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.820
5 | 2.807 | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q | svo_hdmi_inst/tmds_serdes[1]/RESET | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.820
6 | 2.807 | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q | svo_hdmi_inst/tmds_serdes[0]/RESET | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.820
7 | 4.775 | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q | svo_hdmi_inst/tmds_serdes[2]/RESET | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_pll/rpll_inst/CLKOUT.default_gen_clk:[F] | -3.968 | -1.971 | 2.820
8 | 4.775 | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q | svo_hdmi_inst/tmds_serdes[1]/RESET | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_pll/rpll_inst/CLKOUT.default_gen_clk:[F] | -3.968 | -1.971 | 2.820
9 | 4.775 | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q | svo_hdmi_inst/tmds_serdes[0]/RESET | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R] | u_pll/rpll_inst/CLKOUT.default_gen_clk:[F] | -3.968 | -1.971 | 2.820

## Minimum Pulse Width Table:

Number | Slack | Actual Width | Required Width | Type | Clock | Objects
--- | --- | --- | --- | --- | --- | ---

#### Report Command:report_min_pulse_width -nworst 10 -detail

1 | 7.300 | 8.550 | 1.250 | Low Pulse Width | cpuclk | spi_1/divider_12_s0
2 | 7.300 | 8.550 | 1.250 | Low Pulse Width | cpuclk | spi_1/divider_10_s0
3 | 7.300 | 8.550 | 1.250 | Low Pulse Width | cpuclk | spi_1/divider_6_s0
4 | 7.300 | 8.550 | 1.250 | Low Pulse Width | cpuclk | spi_1/data_tx_7_s0
5 | 7.300 | 8.550 | 1.250 | Low Pulse Width | cpuclk | spi_1/data_rx_3_s0
6 | 7.300 | 8.550 | 1.250 | Low Pulse Width | cpuclk | serial_1/txdata_2_s0
7 | 7.300 | 8.550 | 1.250 | Low Pulse Width | cpuclk | test1/r0_5_s0
8 | 7.300 | 8.550 | 1.250 | Low Pulse Width | cpuclk | test1/toneB/divider_11_s0
9 | 7.300 | 8.550 | 1.250 | Low Pulse Width | cpuclk | svo_hdmi_inst/svo_tcard/bramwraddr_11_s0
10 | 7.300 | 8.550 | 1.250 | Low Pulse Width | cpuclk | svo_hdmi_inst/svo_tcard/bramwraddr_12_s0

## Timing Report By Analysis Type:

### Setup Analysis Report

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | -14.411
Data Arrival Time | 37.495
Data Required Time | 23.084
From | test1/wng1/noiseact_s0
To | test1/dac1/outshr_10_s0
Launch Clk | cpuclk:[R]
Latch Clk | cpuclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
2.088 | 2.088 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
3.484 | 1.396 | tNET | RR | 1 | R16C16[2][A] | test1/wng1/noiseact_s0/CLK
3.942 | 0.458 | tC2Q | RF | 27 | R16C16[2][A] | test1/wng1/noiseact_s0/Q
4.754 | 0.811 | tNET | FF | 1 | R17C14[1][A] | test1/w001_11_s3/I1
5.786 | 1.032 | tINS | FF | 6 | R17C14[1][A] | test1/w001_11_s3/F
6.646 | 0.861 | tNET | FF | 1 | R17C17[1][B] | test1/w001_6_s6/I3
7.272 | 0.626 | tINS | FF | 3 | R17C17[1][B] | test1/w001_6_s6/F
9.057 | 1.785 | tNET | FF | 1 | R20C14[0][B] | test1/w001_6_s7/I0
9.683 | 0.626 | tINS | FF | 2 | R20C14[0][B] | test1/w001_6_s7/F
10.978 | 1.294 | tNET | FF | 2 | R23C13[0][A] | test1/n376_s/I0
11.706 | 0.728 | tINS | FR | 1 | R23C13[0][A] | test1/n376_s/SUM
12.125 | 0.419 | tNET | RR | 1 | R22C13[0][A] | test1/w002_6_s3/I0
12.947 | 0.822 | tINS | RF | 2 | R22C13[0][A] | test1/w002_6_s3/F
13.442 | 0.496 | tNET | FF | 1 | R22C14[1][A] | test1/w002_6_s0/I1
14.068 | 0.626 | tINS | FF | 2 | R22C14[1][A] | test1/w002_6_s0/F
15.208 | 1.140 | tNET | FF | 2 | R21C16[0][A] | test1/n552_s/I0
15.936 | 0.728 | tINS | FR | 2 | R21C16[0][A] | test1/n552_s/SUM
16.724 | 0.788 | tNET | RR | 1 | R22C14[2][A] | test1/w003_6_s7/I0
17.349 | 0.625 | tINS | RR | 2 | R22C14[2][A] | test1/w003_6_s7/F
17.770 | 0.421 | tNET | RR | 1 | R21C14[3][B] | test1/w003_6_s3/I3
18.396 | 0.626 | tINS | RF | 2 | R21C14[3][B] | test1/w003_6_s3/F
19.205 | 0.809 | tNET | FF | 1 | R18C14[1][A] | test1/w003_6_s1/I3
19.831 | 0.626 | tINS | FF | 2 | R18C14[1][A] | test1/w003_6_s1/F
19.842 | 0.011 | tNET | FF | 1 | R18C14[3][A] | test1/w003_6_s0/I2
20.468 | 0.626 | tINS | FF | 1 | R18C14[3][A] | test1/w003_6_s0/F
21.773 | 1.305 | tNET | FF | 2 | R20C16[1][A] | test1/n670_1_s/I0
22.767 | 0.994 | tINS | FR | 1 | R20C16[1][A] | test1/n670_1_s/SUM
23.186 | 0.419 | tNET | RR | 1 | R21C16[3][B] | test1/w004_6_s3/I0
24.218 | 1.032 | tINS | RF | 3 | R21C16[3][B] | test1/w004_6_s3/F
25.517 | 1.299 | tNET | FF | 1 | R18C14[3][B] | test1/w004_6_s0/I3
26.578 | 1.061 | tINS | FR | 1 | R18C14[3][B] | test1/w004_6_s0/F
26.997 | 0.419 | tNET | RR | 2 | R18C13[1][A] | test1/n704_1_s/I0
27.955 | 0.958 | tINS | RF | 1 | R18C13[1][A] | test1/n704_1_s/COUT
27.955 | 0.000 | tNET | FF | 2 | R18C13[1][B] | test1/n703_1_s/CIN
28.012 | 0.057 | tINS | FF | 1 | R18C13[1][B] | test1/n703_1_s/COUT
28.012 | 0.000 | tNET | FF | 2 | R18C13[2][A] | test1/n702_1_s/CIN
28.069 | 0.057 | tINS | FF | 1 | R18C13[2][A] | test1/n702_1_s/COUT
28.069 | 0.000 | tNET | FF | 2 | R18C13[2][B] | test1/n701_1_s/CIN
28.632 | 0.563 | tINS | FF | 1 | R18C13[2][B] | test1/n701_1_s/SUM
28.637 | 0.005 | tNET | FF | 1 | R18C13[3][B] | test1/w005_9_s7/I0
29.669 | 1.032 | tINS | FF | 2 | R18C13[3][B] | test1/w005_9_s7/F
31.134 | 1.465 | tNET | FF | 1 | R22C15[3][B] | test1/w005_9_s0/I2
31.760 | 0.626 | tINS | FF | 1 | R22C15[3][B] | test1/w005_9_s0/F
33.049 | 1.289 | tNET | FF | 2 | R18C15[2][B] | test1/n735_1_s/I0
34.007 | 0.958 | tINS | FF | 1 | R18C15[2][B] | test1/n735_1_s/COUT
34.007 | 0.000 | tNET | FF | 2 | R18C16[0][A] | test1/n734_1_s/CIN
34.535 | 0.528 | tINS | FR | 1 | R18C16[0][A] | test1/n734_1_s/SUM
34.954 | 0.419 | tNET | RR | 1 | R17C16[0][B] | test1/dac1/n19_s1/I2
35.580 | 0.626 | tINS | RF | 1 | R17C16[0][B] | test1/dac1/n19_s1/F
36.869 | 1.289 | tNET | FF | 1 | R20C17[1][A] | test1/dac1/n19_s0/I0
37.495 | 0.626 | tINS | FF | 1 | R20C17[1][A] | test1/dac1/n19_s0/F
37.495 | 0.000 | tNET | FF | 1 | R20C17[1][A] | test1/dac1/outshr_10_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | cpuclk
20.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
22.088 | 2.088 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
23.484 | 1.396 | tNET | RR | 1 | R20C17[1][A] | test1/dac1/outshr_10_s0/CLK
23.084 | -0.400 | tSu |  | 1 | R20C17[1][A] | test1/dac1/outshr_10_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 20.000
Logic Level | 23
Arrival Clock Path Delay | cell: 2.088, 59.930%; route: 1.396, 40.070%
Arrival Data Path Delay | cell: 16.809, 49.423%; route: 16.743, 49.230%; tC2Q: 0.458, 1.348%
Required Clock Path Delay | cell: 2.088, 59.930%; route: 1.396, 40.070%

### Path2

Path Summary:

Slack | -14.218
Data Arrival Time | 37.303
Data Required Time | 23.084
From | test1/env1/env_amp_2_s0
To | test1/dac1/outshr_11_s0
Launch Clk | cpuclk:[R]
Latch Clk | cpuclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
2.088 | 2.088 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
3.484 | 1.396 | tNET | RR | 1 | R20C9[2][A] | test1/env1/env_amp_2_s0/CLK
3.942 | 0.458 | tC2Q | RF | 8 | R20C9[2][A] | test1/env1/env_amp_2_s0/Q
5.717 | 1.775 | tNET | FF | 1 | R17C16[1][B] | test1/ampA_2_s0/I1
6.343 | 0.626 | tINS | FF | 6 | R17C16[1][B] | test1/ampA_2_s0/F
7.158 | 0.815 | tNET | FF | 1 | R16C15[3][B] | test1/w001_8_s2/I0
8.190 | 1.032 | tINS | FF | 1 | R16C15[3][B] | test1/w001_8_s2/F
8.196 | 0.005 | tNET | FF | 1 | R16C15[3][A] | test1/w001_8_s1/I0
9.228 | 1.032 | tINS | FF | 3 | R16C15[3][A] | test1/w001_8_s1/F
9.729 | 0.501 | tNET | FF | 1 | R18C15[3][B] | test1/w001_8_s0/I2
10.355 | 0.626 | tINS | FF | 2 | R18C15[3][B] | test1/w001_8_s0/F
11.814 | 1.459 | tNET | FF | 2 | R23C14[2][A] | test1/n366_1_s/I0
12.797 | 0.983 | tINS | FF | 2 | R23C14[2][A] | test1/n366_1_s/SUM
13.940 | 1.144 | tNET | FF | 1 | R17C14[2][B] | test1/w002_8_s4/I0
14.565 | 0.625 | tINS | FR | 1 | R17C14[2][B] | test1/w002_8_s4/F
14.984 | 0.419 | tNET | RR | 1 | R17C15[2][B] | test1/w002_8_s0/I3
16.083 | 1.099 | tINS | RF | 2 | R17C15[2][B] | test1/w002_8_s0/F
17.378 | 1.294 | tNET | FF | 2 | R21C16[1][A] | test1/n550_s/I0
18.423 | 1.045 | tINS | FF | 1 | R21C16[1][A] | test1/n550_s/COUT
18.423 | 0.000 | tNET | FF | 2 | R21C16[1][B] | test1/n549_s/CIN
18.480 | 0.057 | tINS | FF | 1 | R21C16[1][B] | test1/n549_s/COUT
18.480 | 0.000 | tNET | FF | 2 | R21C16[2][A] | test1/n548_s/CIN
19.008 | 0.528 | tINS | FR | 2 | R21C16[2][A] | test1/n548_s/SUM
19.431 | 0.423 | tNET | RR | 1 | R21C15[3][A] | test1/w003_10_s4/I2
20.492 | 1.061 | tINS | RR | 2 | R21C15[3][A] | test1/w003_10_s4/F
20.914 | 0.423 | tNET | RR | 1 | R21C14[0][B] | test1/w003_10_s2/I3
21.540 | 0.626 | tINS | RF | 2 | R21C14[0][B] | test1/w003_10_s2/F
22.520 | 0.979 | tNET | FF | 1 | R17C14[3][B] | test1/w003_10_s0/I2
23.552 | 1.032 | tINS | FF | 2 | R17C14[3][B] | test1/w003_10_s0/F
25.331 | 1.779 | tNET | FF | 2 | R20C17[0][A] | test1/n666_1_s/I0
26.314 | 0.983 | tINS | FF | 2 | R20C17[0][A] | test1/n666_1_s/SUM
28.098 | 1.785 | tNET | FF | 1 | R17C14[3][A] | test1/w004_10_s1/I1
28.900 | 0.802 | tINS | FR | 1 | R17C14[3][A] | test1/w004_10_s1/F
29.319 | 0.419 | tNET | RR | 2 | R18C14[0][A] | test1/n700_1_s/I0
30.277 | 0.958 | tINS | RF | 1 | R18C14[0][A] | test1/n700_1_s/COUT
30.277 | 0.000 | tNET | FF | 2 | R18C14[0][B] | test1/n699_1_s/CIN
30.840 | 0.563 | tINS | FF | 1 | R18C14[0][B] | test1/n699_1_s/SUM
31.330 | 0.490 | tNET | FF | 1 | R20C14[2][B] | test1/w005_11_s3/I0
32.362 | 1.032 | tINS | FF | 2 | R20C14[2][B] | test1/w005_11_s3/F
32.857 | 0.495 | tNET | FF | 1 | R20C16[3][A] | test1/w005_11_s0/I3
33.889 | 1.032 | tINS | FF | 1 | R20C16[3][A] | test1/w005_11_s0/F
34.693 | 0.804 | tNET | FF | 2 | R18C16[0][B] | test1/n733_1_s/I0
35.676 | 0.983 | tINS | FF | 1 | R18C16[0][B] | test1/n733_1_s/SUM
36.481 | 0.804 | tNET | FF | 1 | R20C17[1][B] | test1/dac1/n18_s1/I1
37.303 | 0.822 | tINS | FF | 1 | R20C17[1][B] | test1/dac1/n18_s1/F
37.303 | 0.000 | tNET | FF | 1 | R20C17[1][B] | test1/dac1/outshr_11_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | cpuclk
20.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
22.088 | 2.088 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
23.484 | 1.396 | tNET | RR | 1 | R20C17[1][B] | test1/dac1/outshr_11_s0/CLK
23.084 | -0.400 | tSu |  | 1 | R20C17[1][B] | test1/dac1/outshr_11_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 20.000
Logic Level | 21
Arrival Clock Path Delay | cell: 2.088, 59.930%; route: 1.396, 40.070%
Arrival Data Path Delay | cell: 17.547, 51.886%; route: 15.813, 46.759%; tC2Q: 0.458, 1.355%
Required Clock Path Delay | cell: 2.088, 59.930%; route: 1.396, 40.070%

### Path3

Path Summary:

Slack | -14.175
Data Arrival Time | 37.259
Data Required Time | 23.084
From | test1/wng1/noiseact_s0
To | test1/dac1/outshr_9_s0
Launch Clk | cpuclk:[R]
Latch Clk | cpuclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
2.088 | 2.088 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
3.484 | 1.396 | tNET | RR | 1 | R16C16[2][A] | test1/wng1/noiseact_s0/CLK
3.942 | 0.458 | tC2Q | RF | 27 | R16C16[2][A] | test1/wng1/noiseact_s0/Q
4.754 | 0.811 | tNET | FF | 1 | R17C14[1][A] | test1/w001_11_s3/I1
5.786 | 1.032 | tINS | FF | 6 | R17C14[1][A] | test1/w001_11_s3/F
6.646 | 0.861 | tNET | FF | 1 | R17C17[1][B] | test1/w001_6_s6/I3
7.272 | 0.626 | tINS | FF | 3 | R17C17[1][B] | test1/w001_6_s6/F
9.057 | 1.785 | tNET | FF | 1 | R20C14[0][B] | test1/w001_6_s7/I0
9.683 | 0.626 | tINS | FF | 2 | R20C14[0][B] | test1/w001_6_s7/F
10.978 | 1.294 | tNET | FF | 2 | R23C13[0][A] | test1/n376_s/I0
11.706 | 0.728 | tINS | FR | 1 | R23C13[0][A] | test1/n376_s/SUM
12.125 | 0.419 | tNET | RR | 1 | R22C13[0][A] | test1/w002_6_s3/I0
12.947 | 0.822 | tINS | RF | 2 | R22C13[0][A] | test1/w002_6_s3/F
13.442 | 0.496 | tNET | FF | 1 | R22C14[1][A] | test1/w002_6_s0/I1
14.068 | 0.626 | tINS | FF | 2 | R22C14[1][A] | test1/w002_6_s0/F
15.208 | 1.140 | tNET | FF | 2 | R21C16[0][A] | test1/n552_s/I0
15.936 | 0.728 | tINS | FR | 2 | R21C16[0][A] | test1/n552_s/SUM
16.724 | 0.788 | tNET | RR | 1 | R22C14[2][A] | test1/w003_6_s7/I0
17.349 | 0.625 | tINS | RR | 2 | R22C14[2][A] | test1/w003_6_s7/F
17.770 | 0.421 | tNET | RR | 1 | R21C14[3][B] | test1/w003_6_s3/I3
18.396 | 0.626 | tINS | RF | 2 | R21C14[3][B] | test1/w003_6_s3/F
19.205 | 0.809 | tNET | FF | 1 | R18C14[1][A] | test1/w003_6_s1/I3
19.831 | 0.626 | tINS | FF | 2 | R18C14[1][A] | test1/w003_6_s1/F
19.842 | 0.011 | tNET | FF | 1 | R18C14[3][A] | test1/w003_6_s0/I2
20.468 | 0.626 | tINS | FF | 1 | R18C14[3][A] | test1/w003_6_s0/F
21.773 | 1.305 | tNET | FF | 2 | R20C16[1][A] | test1/n670_1_s/I0
22.767 | 0.994 | tINS | FR | 1 | R20C16[1][A] | test1/n670_1_s/SUM
23.186 | 0.419 | tNET | RR | 1 | R21C16[3][B] | test1/w004_6_s3/I0
24.218 | 1.032 | tINS | RF | 3 | R21C16[3][B] | test1/w004_6_s3/F
25.517 | 1.299 | tNET | FF | 1 | R18C14[3][B] | test1/w004_6_s0/I3
26.578 | 1.061 | tINS | FR | 1 | R18C14[3][B] | test1/w004_6_s0/F
26.997 | 0.419 | tNET | RR | 2 | R18C13[1][A] | test1/n704_1_s/I0
27.955 | 0.958 | tINS | RF | 1 | R18C13[1][A] | test1/n704_1_s/COUT
27.955 | 0.000 | tNET | FF | 2 | R18C13[1][B] | test1/n703_1_s/CIN
28.012 | 0.057 | tINS | FF | 1 | R18C13[1][B] | test1/n703_1_s/COUT
28.012 | 0.000 | tNET | FF | 2 | R18C13[2][A] | test1/n702_1_s/CIN
28.069 | 0.057 | tINS | FF | 1 | R18C13[2][A] | test1/n702_1_s/COUT
28.069 | 0.000 | tNET | FF | 2 | R18C13[2][B] | test1/n701_1_s/CIN
28.632 | 0.563 | tINS | FF | 1 | R18C13[2][B] | test1/n701_1_s/SUM
28.637 | 0.005 | tNET | FF | 1 | R18C13[3][B] | test1/w005_9_s7/I0
29.669 | 1.032 | tINS | FF | 2 | R18C13[3][B] | test1/w005_9_s7/F
31.134 | 1.465 | tNET | FF | 1 | R22C15[3][B] | test1/w005_9_s0/I2
31.760 | 0.626 | tINS | FF | 1 | R22C15[3][B] | test1/w005_9_s0/F
33.049 | 1.289 | tNET | FF | 2 | R18C15[2][B] | test1/n735_1_s/I0
34.032 | 0.983 | tINS | FF | 1 | R18C15[2][B] | test1/n735_1_s/SUM
35.007 | 0.975 | tNET | FF | 1 | R22C15[1][A] | test1/dac1/n20_s1/I2
35.633 | 0.626 | tINS | FF | 1 | R22C15[1][A] | test1/dac1/n20_s1/F
36.437 | 0.804 | tNET | FF | 1 | R22C17[0][A] | test1/dac1/n20_s0/I1
37.259 | 0.822 | tINS | FF | 1 | R22C17[0][A] | test1/dac1/n20_s0/F
37.259 | 0.000 | tNET | FF | 1 | R22C17[0][A] | test1/dac1/outshr_9_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | cpuclk
20.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
22.088 | 2.088 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
23.484 | 1.396 | tNET | RR | 1 | R22C17[0][A] | test1/dac1/outshr_9_s0/CLK
23.084 | -0.400 | tSu |  | 1 | R22C17[0][A] | test1/dac1/outshr_9_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 20.000
Logic Level | 22
Arrival Clock Path Delay | cell: 2.088, 59.930%; route: 1.396, 40.070%
Arrival Data Path Delay | cell: 16.502, 48.859%; route: 16.815, 49.784%; tC2Q: 0.458, 1.357%
Required Clock Path Delay | cell: 2.088, 59.930%; route: 1.396, 40.070%

### Path4

Path Summary:

Slack | -11.987
Data Arrival Time | 35.071
Data Required Time | 23.084
From | test1/wng1/noiseact_s0
To | test1/dac1/outshr_8_s0
Launch Clk | cpuclk:[R]
Latch Clk | cpuclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
2.088 | 2.088 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
3.484 | 1.396 | tNET | RR | 1 | R16C16[2][A] | test1/wng1/noiseact_s0/CLK
3.942 | 0.458 | tC2Q | RF | 27 | R16C16[2][A] | test1/wng1/noiseact_s0/Q
4.754 | 0.811 | tNET | FF | 1 | R17C14[1][A] | test1/w001_11_s3/I1
5.786 | 1.032 | tINS | FF | 6 | R17C14[1][A] | test1/w001_11_s3/F
6.646 | 0.861 | tNET | FF | 1 | R17C17[1][B] | test1/w001_6_s6/I3
7.272 | 0.626 | tINS | FF | 3 | R17C17[1][B] | test1/w001_6_s6/F
9.057 | 1.785 | tNET | FF | 1 | R20C14[0][B] | test1/w001_6_s7/I0
9.683 | 0.626 | tINS | FF | 2 | R20C14[0][B] | test1/w001_6_s7/F
10.978 | 1.294 | tNET | FF | 2 | R23C13[0][A] | test1/n376_s/I0
11.706 | 0.728 | tINS | FR | 1 | R23C13[0][A] | test1/n376_s/SUM
12.125 | 0.419 | tNET | RR | 1 | R22C13[0][A] | test1/w002_6_s3/I0
12.947 | 0.822 | tINS | RF | 2 | R22C13[0][A] | test1/w002_6_s3/F
13.442 | 0.496 | tNET | FF | 1 | R22C14[1][A] | test1/w002_6_s0/I1
14.068 | 0.626 | tINS | FF | 2 | R22C14[1][A] | test1/w002_6_s0/F
15.208 | 1.140 | tNET | FF | 2 | R21C16[0][A] | test1/n552_s/I0
15.936 | 0.728 | tINS | FR | 2 | R21C16[0][A] | test1/n552_s/SUM
16.724 | 0.788 | tNET | RR | 1 | R22C14[2][A] | test1/w003_6_s7/I0
17.349 | 0.625 | tINS | RR | 2 | R22C14[2][A] | test1/w003_6_s7/F
17.770 | 0.421 | tNET | RR | 1 | R21C14[3][B] | test1/w003_6_s3/I3
18.396 | 0.626 | tINS | RF | 2 | R21C14[3][B] | test1/w003_6_s3/F
19.205 | 0.809 | tNET | FF | 1 | R18C14[1][A] | test1/w003_6_s1/I3
19.831 | 0.626 | tINS | FF | 2 | R18C14[1][A] | test1/w003_6_s1/F
19.842 | 0.011 | tNET | FF | 1 | R18C14[3][A] | test1/w003_6_s0/I2
20.468 | 0.626 | tINS | FF | 1 | R18C14[3][A] | test1/w003_6_s0/F
21.773 | 1.305 | tNET | FF | 2 | R20C16[1][A] | test1/n670_1_s/I0
22.767 | 0.994 | tINS | FR | 1 | R20C16[1][A] | test1/n670_1_s/SUM
23.186 | 0.419 | tNET | RR | 1 | R21C16[3][B] | test1/w004_6_s3/I0
24.218 | 1.032 | tINS | RF | 3 | R21C16[3][B] | test1/w004_6_s3/F
25.517 | 1.299 | tNET | FF | 1 | R18C14[3][B] | test1/w004_6_s0/I3
26.578 | 1.061 | tINS | FR | 1 | R18C14[3][B] | test1/w004_6_s0/F
26.997 | 0.419 | tNET | RR | 2 | R18C13[1][A] | test1/n704_1_s/I0
27.955 | 0.958 | tINS | RF | 1 | R18C13[1][A] | test1/n704_1_s/COUT
27.955 | 0.000 | tNET | FF | 2 | R18C13[1][B] | test1/n703_1_s/CIN
28.518 | 0.563 | tINS | FF | 1 | R18C13[1][B] | test1/n703_1_s/SUM
28.523 | 0.005 | tNET | FF | 1 | R18C13[3][A] | test1/w005_7_s4/I1
29.622 | 1.099 | tINS | FF | 2 | R18C13[3][A] | test1/w005_7_s4/F
30.432 | 0.810 | tNET | FF | 2 | R18C15[1][B] | test1/n737_1_s/I0
31.390 | 0.958 | tINS | FF | 1 | R18C15[1][B] | test1/n737_1_s/COUT
31.390 | 0.000 | tNET | FF | 2 | R18C15[2][A] | test1/n736_1_s/CIN
31.953 | 0.563 | tINS | FF | 1 | R18C15[2][A] | test1/n736_1_s/SUM
32.928 | 0.975 | tNET | FF | 1 | R22C15[3][A] | test1/dac1/n21_s3/I0
33.553 | 0.625 | tINS | FR | 1 | R22C15[3][A] | test1/dac1/n21_s3/F
33.972 | 0.419 | tNET | RR | 1 | R22C16[0][B] | test1/dac1/n21_s0/I0
35.071 | 1.099 | tINS | RF | 1 | R22C16[0][B] | test1/dac1/n21_s0/F
35.071 | 0.000 | tNET | FF | 1 | R22C16[0][B] | test1/dac1/outshr_8_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | cpuclk
20.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
22.088 | 2.088 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
23.484 | 1.396 | tNET | RR | 1 | R22C16[0][B] | test1/dac1/outshr_8_s0/CLK
23.084 | -0.400 | tSu |  | 1 | R22C16[0][B] | test1/dac1/outshr_8_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 20.000
Logic Level | 22
Arrival Clock Path Delay | cell: 2.088, 59.930%; route: 1.396, 40.070%
Arrival Data Path Delay | cell: 16.643, 52.690%; route: 14.485, 45.859%; tC2Q: 0.458, 1.451%
Required Clock Path Delay | cell: 2.088, 59.930%; route: 1.396, 40.070%

### Path5

Path Summary:

Slack | -11.480
Data Arrival Time | 34.564
Data Required Time | 23.084
From | test1/wng1/noiseact_s0
To | test1/dac1/outshr_7_s0
Launch Clk | cpuclk:[R]
Latch Clk | cpuclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
2.088 | 2.088 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
3.484 | 1.396 | tNET | RR | 1 | R16C16[2][A] | test1/wng1/noiseact_s0/CLK
3.942 | 0.458 | tC2Q | RF | 27 | R16C16[2][A] | test1/wng1/noiseact_s0/Q
4.754 | 0.811 | tNET | FF | 1 | R17C14[1][A] | test1/w001_11_s3/I1
5.786 | 1.032 | tINS | FF | 6 | R17C14[1][A] | test1/w001_11_s3/F
6.646 | 0.861 | tNET | FF | 1 | R17C17[1][B] | test1/w001_6_s6/I3
7.272 | 0.626 | tINS | FF | 3 | R17C17[1][B] | test1/w001_6_s6/F
9.057 | 1.785 | tNET | FF | 1 | R20C14[0][B] | test1/w001_6_s7/I0
9.683 | 0.626 | tINS | FF | 2 | R20C14[0][B] | test1/w001_6_s7/F
10.978 | 1.294 | tNET | FF | 2 | R23C13[0][A] | test1/n376_s/I0
11.706 | 0.728 | tINS | FR | 1 | R23C13[0][A] | test1/n376_s/SUM
12.125 | 0.419 | tNET | RR | 1 | R22C13[0][A] | test1/w002_6_s3/I0
12.947 | 0.822 | tINS | RF | 2 | R22C13[0][A] | test1/w002_6_s3/F
13.442 | 0.496 | tNET | FF | 1 | R22C14[1][A] | test1/w002_6_s0/I1
14.068 | 0.626 | tINS | FF | 2 | R22C14[1][A] | test1/w002_6_s0/F
15.208 | 1.140 | tNET | FF | 2 | R21C16[0][A] | test1/n552_s/I0
15.936 | 0.728 | tINS | FR | 2 | R21C16[0][A] | test1/n552_s/SUM
16.724 | 0.788 | tNET | RR | 1 | R22C14[2][A] | test1/w003_6_s7/I0
17.349 | 0.625 | tINS | RR | 2 | R22C14[2][A] | test1/w003_6_s7/F
17.770 | 0.421 | tNET | RR | 1 | R21C14[3][B] | test1/w003_6_s3/I3
18.396 | 0.626 | tINS | RF | 2 | R21C14[3][B] | test1/w003_6_s3/F
19.205 | 0.809 | tNET | FF | 1 | R18C14[1][A] | test1/w003_6_s1/I3
19.831 | 0.626 | tINS | FF | 2 | R18C14[1][A] | test1/w003_6_s1/F
19.842 | 0.011 | tNET | FF | 1 | R18C14[3][A] | test1/w003_6_s0/I2
20.468 | 0.626 | tINS | FF | 1 | R18C14[3][A] | test1/w003_6_s0/F
21.773 | 1.305 | tNET | FF | 2 | R20C16[1][A] | test1/n670_1_s/I0
22.767 | 0.994 | tINS | FR | 1 | R20C16[1][A] | test1/n670_1_s/SUM
23.186 | 0.419 | tNET | RR | 1 | R21C16[3][B] | test1/w004_6_s3/I0
24.218 | 1.032 | tINS | RF | 3 | R21C16[3][B] | test1/w004_6_s3/F
25.517 | 1.299 | tNET | FF | 1 | R18C14[3][B] | test1/w004_6_s0/I3
26.578 | 1.061 | tINS | FR | 1 | R18C14[3][B] | test1/w004_6_s0/F
26.997 | 0.419 | tNET | RR | 2 | R18C13[1][A] | test1/n704_1_s/I0
27.955 | 0.958 | tINS | RF | 1 | R18C13[1][A] | test1/n704_1_s/COUT
27.955 | 0.000 | tNET | FF | 2 | R18C13[1][B] | test1/n703_1_s/CIN
28.518 | 0.563 | tINS | FF | 1 | R18C13[1][B] | test1/n703_1_s/SUM
28.523 | 0.005 | tNET | FF | 1 | R18C13[3][A] | test1/w005_7_s4/I1
29.622 | 1.099 | tINS | FF | 2 | R18C13[3][A] | test1/w005_7_s4/F
30.432 | 0.810 | tNET | FF | 2 | R18C15[1][B] | test1/n737_1_s/I0
31.415 | 0.983 | tINS | FF | 1 | R18C15[1][B] | test1/n737_1_s/SUM
32.704 | 1.289 | tNET | FF | 1 | R22C15[2][A] | test1/dac1/n22_s1/I1
33.736 | 1.032 | tINS | FF | 1 | R22C15[2][A] | test1/dac1/n22_s1/F
33.742 | 0.005 | tNET | FF | 1 | R22C15[1][B] | test1/dac1/n22_s0/I1
34.564 | 0.822 | tINS | FF | 1 | R22C15[1][B] | test1/dac1/n22_s0/F
34.564 | 0.000 | tNET | FF | 1 | R22C15[1][B] | test1/dac1/outshr_7_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | cpuclk
20.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
22.088 | 2.088 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
23.484 | 1.396 | tNET | RR | 1 | R22C15[1][B] | test1/dac1/outshr_7_s0/CLK
23.084 | -0.400 | tSu |  | 1 | R22C15[1][B] | test1/dac1/outshr_7_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 20.000
Logic Level | 21
Arrival Clock Path Delay | cell: 2.088, 59.930%; route: 1.396, 40.070%
Arrival Data Path Delay | cell: 16.235, 52.237%; route: 14.386, 46.289%; tC2Q: 0.458, 1.475%
Required Clock Path Delay | cell: 2.088, 59.930%; route: 1.396, 40.070%

### Path6

Path Summary:

Slack | -10.080
Data Arrival Time | 33.164
Data Required Time | 23.084
From | test1/wng1/noiseact_s0
To | test1/dac1/outshr_6_s0
Launch Clk | cpuclk:[R]
Latch Clk | cpuclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
2.088 | 2.088 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
3.484 | 1.396 | tNET | RR | 1 | R16C16[2][A] | test1/wng1/noiseact_s0/CLK
3.942 | 0.458 | tC2Q | RF | 27 | R16C16[2][A] | test1/wng1/noiseact_s0/Q
4.754 | 0.811 | tNET | FF | 1 | R17C14[1][A] | test1/w001_11_s3/I1
5.786 | 1.032 | tINS | FF | 6 | R17C14[1][A] | test1/w001_11_s3/F
6.646 | 0.861 | tNET | FF | 1 | R17C17[1][B] | test1/w001_6_s6/I3
7.272 | 0.626 | tINS | FF | 3 | R17C17[1][B] | test1/w001_6_s6/F
9.057 | 1.785 | tNET | FF | 1 | R20C14[0][B] | test1/w001_6_s7/I0
9.683 | 0.626 | tINS | FF | 2 | R20C14[0][B] | test1/w001_6_s7/F
10.978 | 1.294 | tNET | FF | 2 | R23C13[0][A] | test1/n376_s/I0
11.706 | 0.728 | tINS | FR | 1 | R23C13[0][A] | test1/n376_s/SUM
12.125 | 0.419 | tNET | RR | 1 | R22C13[0][A] | test1/w002_6_s3/I0
12.947 | 0.822 | tINS | RF | 2 | R22C13[0][A] | test1/w002_6_s3/F
13.442 | 0.496 | tNET | FF | 1 | R22C14[1][A] | test1/w002_6_s0/I1
14.068 | 0.626 | tINS | FF | 2 | R22C14[1][A] | test1/w002_6_s0/F
15.208 | 1.140 | tNET | FF | 2 | R21C16[0][A] | test1/n552_s/I0
15.936 | 0.728 | tINS | FR | 2 | R21C16[0][A] | test1/n552_s/SUM
16.724 | 0.788 | tNET | RR | 1 | R22C14[2][A] | test1/w003_6_s7/I0
17.349 | 0.625 | tINS | RR | 2 | R22C14[2][A] | test1/w003_6_s7/F
17.770 | 0.421 | tNET | RR | 1 | R21C14[3][B] | test1/w003_6_s3/I3
18.396 | 0.626 | tINS | RF | 2 | R21C14[3][B] | test1/w003_6_s3/F
19.205 | 0.809 | tNET | FF | 1 | R18C14[1][A] | test1/w003_6_s1/I3
19.831 | 0.626 | tINS | FF | 2 | R18C14[1][A] | test1/w003_6_s1/F
19.842 | 0.011 | tNET | FF | 1 | R18C14[3][A] | test1/w003_6_s0/I2
20.468 | 0.626 | tINS | FF | 1 | R18C14[3][A] | test1/w003_6_s0/F
21.773 | 1.305 | tNET | FF | 2 | R20C16[1][A] | test1/n670_1_s/I0
22.767 | 0.994 | tINS | FR | 1 | R20C16[1][A] | test1/n670_1_s/SUM
23.186 | 0.419 | tNET | RR | 1 | R21C16[3][B] | test1/w004_6_s3/I0
24.218 | 1.032 | tINS | RF | 3 | R21C16[3][B] | test1/w004_6_s3/F
25.517 | 1.299 | tNET | FF | 1 | R18C14[3][B] | test1/w004_6_s0/I3
26.578 | 1.061 | tINS | FR | 1 | R18C14[3][B] | test1/w004_6_s0/F
26.997 | 0.419 | tNET | RR | 2 | R18C13[1][A] | test1/n704_1_s/I0
27.991 | 0.994 | tINS | RR | 2 | R18C13[1][A] | test1/n704_1_s/SUM
28.414 | 0.423 | tNET | RR | 1 | R18C14[1][B] | test1/w005_6_s0/I2
29.216 | 0.802 | tINS | RR | 1 | R18C14[1][B] | test1/w005_6_s0/F
29.635 | 0.419 | tNET | RR | 2 | R18C15[1][A] | test1/n738_1_s/I0
30.618 | 0.983 | tINS | RF | 1 | R18C15[1][A] | test1/n738_1_s/SUM
31.907 | 1.289 | tNET | FF | 1 | R22C16[1][A] | test1/dac1/n23_s1/I2
32.533 | 0.626 | tINS | FF | 1 | R22C16[1][A] | test1/dac1/n23_s1/F
32.538 | 0.005 | tNET | FF | 1 | R22C16[1][B] | test1/dac1/n23_s0/I0
33.164 | 0.626 | tINS | FF | 1 | R22C16[1][B] | test1/dac1/n23_s0/F
33.164 | 0.000 | tNET | FF | 1 | R22C16[1][B] | test1/dac1/outshr_6_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | cpuclk
20.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
22.088 | 2.088 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
23.484 | 1.396 | tNET | RR | 1 | R22C16[1][B] | test1/dac1/outshr_6_s0/CLK
23.084 | -0.400 | tSu |  | 1 | R22C16[1][B] | test1/dac1/outshr_6_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 20.000
Logic Level | 20
Arrival Clock Path Delay | cell: 2.088, 59.930%; route: 1.396, 40.070%
Arrival Data Path Delay | cell: 14.809, 49.895%; route: 14.413, 48.560%; tC2Q: 0.458, 1.544%
Required Clock Path Delay | cell: 2.088, 59.930%; route: 1.396, 40.070%

### Path7

Path Summary:

Slack | -5.536
Data Arrival Time | 28.620
Data Required Time | 23.084
From | test1/env1/env_amp_0_s0
To | test1/dac1/outshr_5_s0
Launch Clk | cpuclk:[R]
Latch Clk | cpuclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
2.088 | 2.088 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
3.484 | 1.396 | tNET | RR | 1 | R20C8[2][B] | test1/env1/env_amp_0_s0/CLK
3.942 | 0.458 | tC2Q | RF | 14 | R20C8[2][B] | test1/env1/env_amp_0_s0/Q
5.721 | 1.779 | tNET | FF | 1 | R17C17[2][A] | test1/ampA_0_s0/I1
6.347 | 0.626 | tINS | FF | 6 | R17C17[2][A] | test1/ampA_0_s0/F
8.145 | 1.798 | tNET | FF | 1 | R20C14[1][A] | test1/w001_5_s2/I0
9.244 | 1.099 | tINS | FF | 1 | R20C14[1][A] | test1/w001_5_s2/F
10.049 | 0.804 | tNET | FF | 2 | R23C14[0][B] | test1/n369_1_s/I0
11.032 | 0.983 | tINS | FF | 1 | R23C14[0][B] | test1/n369_1_s/SUM
12.485 | 1.453 | tNET | FF | 1 | R18C14[2][A] | test1/w002_5_s0/I2
13.111 | 0.626 | tINS | FF | 2 | R18C14[2][A] | test1/w002_5_s0/F
13.936 | 0.825 | tNET | FF | 2 | R18C16[1][B] | test1/n545_1_s/I0
14.930 | 0.994 | tINS | FR | 1 | R18C16[1][B] | test1/n545_1_s/SUM
14.932 | 0.002 | tNET | RR | 1 | R18C16[3][A] | test1/w003_5_s1/I1
16.031 | 1.099 | tINS | RF | 2 | R18C16[3][A] | test1/w003_5_s1/F
16.857 | 0.825 | tNET | FF | 2 | R20C16[0][B] | test1/n671_1_s/I0
17.851 | 0.994 | tINS | FR | 1 | R20C16[0][B] | test1/n671_1_s/SUM
17.853 | 0.002 | tNET | RR | 1 | R20C16[3][B] | test1/w004_5_s1/I1
18.952 | 1.099 | tINS | RF | 3 | R20C16[3][B] | test1/w004_5_s1/F
20.725 | 1.773 | tNET | FF | 2 | R18C13[0][B] | test1/n705_1_s/I0
21.708 | 0.983 | tINS | FF | 2 | R18C13[0][B] | test1/n705_1_s/SUM
22.203 | 0.495 | tNET | FF | 1 | R18C15[3][A] | test1/w005_5_s1/I1
23.302 | 1.099 | tINS | FF | 1 | R18C15[3][A] | test1/w005_5_s1/F
23.638 | 0.336 | tNET | FF | 2 | R18C15[0][B] | test1/n739_1_s/I0
24.621 | 0.983 | tINS | FF | 1 | R18C15[0][B] | test1/n739_1_s/SUM
26.091 | 1.470 | tNET | FF | 1 | R22C16[2][B] | test1/dac1/n24_s2/I0
26.717 | 0.626 | tINS | FF | 1 | R22C16[2][B] | test1/dac1/n24_s2/F
27.521 | 0.804 | tNET | FF | 1 | R21C17[1][B] | test1/dac1/n24_s0/I3
28.620 | 1.099 | tINS | FF | 1 | R21C17[1][B] | test1/dac1/n24_s0/F
28.620 | 0.000 | tNET | FF | 1 | R21C17[1][B] | test1/dac1/outshr_5_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | cpuclk
20.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
22.088 | 2.088 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
23.484 | 1.396 | tNET | RR | 1 | R21C17[1][B] | test1/dac1/outshr_5_s0/CLK
23.084 | -0.400 | tSu |  | 1 | R21C17[1][B] | test1/dac1/outshr_5_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 20.000
Logic Level | 14
Arrival Clock Path Delay | cell: 2.088, 59.930%; route: 1.396, 40.070%
Arrival Data Path Delay | cell: 12.310, 48.973%; route: 12.368, 49.204%; tC2Q: 0.458, 1.823%
Required Clock Path Delay | cell: 2.088, 59.930%; route: 1.396, 40.070%

### Path8

Path Summary:

Slack | -2.720
Data Arrival Time | 23.877
Data Required Time | 21.157
From | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0
To | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12
Launch Clk | cpuclk:[F]
Latch Clk | svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | 1 | R17C25[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/CLK
14.318 | 0.458 | tC2Q | FF | 16 | R17C25[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q
19.365 | 5.047 | tNET | FF | 1 | R9C21[0][B] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_4/I2
19.991 | 0.626 | tINS | FF | 2 | R9C21[0][B] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_4/F
22.105 | 2.114 | tNET | FF | 1 | R9C8[2][B] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_12/I0
23.166 | 1.061 | tINS | FR | 1 | R9C8[2][B] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_12/F
23.877 | 0.711 | tNET | RR | 1 | BSRAM_R10[1] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12/CEA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | svo_hdmi_inst/svo_tcard/bram_aclock
20.000 | 0.000 | tCL | RR | 23 | R14C26[0][A] | svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.361 | 1.361 | tNET | RR | 1 | BSRAM_R10[1] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12/CLKA
21.331 | -0.030 | tUnc |  |  |  |
21.157 | -0.174 | tSu |  | 1 | BSRAM_R10[1] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12

Path Statistics:

Clock Skew | -2.499
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay | cell: 1.687, 16.841%; route: 7.872, 78.584%; tC2Q: 0.458, 4.575%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.361, 100.000%

### Path9

Path Summary:

Slack | -0.859
Data Arrival Time | 40.927
Data Required Time | 40.068
From | svo_hdmi_inst/svo_tcard/txtmode0/hpixelcount_7_s0
To | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.428 | 0.257 | tNET | FF | 1 | R20C23[0][B] | svo_hdmi_inst/svo_tcard/txtmode0/hpixelcount_7_s0/CLK
20.887 | 0.458 | tC2Q | FF | 3 | R20C23[0][B] | svo_hdmi_inst/svo_tcard/txtmode0/hpixelcount_7_s0/Q
22.036 | 1.149 | tNET | FF | 2 | R18C22[0][A] | svo_hdmi_inst/svo_tcard/txtmode0/memrdpos_4_s/I0
23.081 | 1.045 | tINS | FF | 1 | R18C22[0][A] | svo_hdmi_inst/svo_tcard/txtmode0/memrdpos_4_s/COUT
23.081 | 0.000 | tNET | FF | 2 | R18C22[0][B] | svo_hdmi_inst/svo_tcard/txtmode0/memrdpos_5_s/CIN
23.138 | 0.057 | tINS | FF | 1 | R18C22[0][B] | svo_hdmi_inst/svo_tcard/txtmode0/memrdpos_5_s/COUT
23.138 | 0.000 | tNET | FF | 2 | R18C22[1][A] | svo_hdmi_inst/svo_tcard/txtmode0/memrdpos_6_s/CIN
23.195 | 0.057 | tINS | FF | 1 | R18C22[1][A] | svo_hdmi_inst/svo_tcard/txtmode0/memrdpos_6_s/COUT
23.195 | 0.000 | tNET | FF | 2 | R18C22[1][B] | svo_hdmi_inst/svo_tcard/txtmode0/memrdpos_7_s/CIN
23.252 | 0.057 | tINS | FF | 1 | R18C22[1][B] | svo_hdmi_inst/svo_tcard/txtmode0/memrdpos_7_s/COUT
23.252 | 0.000 | tNET | FF | 2 | R18C22[2][A] | svo_hdmi_inst/svo_tcard/txtmode0/memrdpos_8_s/CIN
23.309 | 0.057 | tINS | FF | 1 | R18C22[2][A] | svo_hdmi_inst/svo_tcard/txtmode0/memrdpos_8_s/COUT
23.309 | 0.000 | tNET | FF | 2 | R18C22[2][B] | svo_hdmi_inst/svo_tcard/txtmode0/memrdpos_9_s/CIN
23.366 | 0.057 | tINS | FF | 1 | R18C22[2][B] | svo_hdmi_inst/svo_tcard/txtmode0/memrdpos_9_s/COUT
23.366 | 0.000 | tNET | FF | 2 | R18C23[0][A] | svo_hdmi_inst/svo_tcard/txtmode0/memrdpos_10_s/CIN
23.423 | 0.057 | tINS | FF | 1 | R18C23[0][A] | svo_hdmi_inst/svo_tcard/txtmode0/memrdpos_10_s/COUT
23.423 | 0.000 | tNET | FF | 2 | R18C23[0][B] | svo_hdmi_inst/svo_tcard/txtmode0/memrdpos_11_s/CIN
23.480 | 0.057 | tINS | FF | 1 | R18C23[0][B] | svo_hdmi_inst/svo_tcard/txtmode0/memrdpos_11_s/COUT
23.480 | 0.000 | tNET | FF | 2 | R18C23[1][A] | svo_hdmi_inst/svo_tcard/txtmode0/memrdpos_12_s/CIN
23.537 | 0.057 | tINS | FF | 2 | R18C23[1][A] | svo_hdmi_inst/svo_tcard/txtmode0/memrdpos_12_s/COUT
25.079 | 1.542 | tNET | FF | 1 | R16C22[0][B] | svo_hdmi_inst/svo_tcard/txtmode0/color_index_mode0_1_s34/I1
26.178 | 1.099 | tINS | FF | 1 | R16C22[0][B] | svo_hdmi_inst/svo_tcard/txtmode0/color_index_mode0_1_s34/F
26.982 | 0.804 | tNET | FF | 1 | R18C22[3][B] | svo_hdmi_inst/svo_tcard/txtmode0/color_index_mode0_1_s29/I2
28.081 | 1.099 | tINS | FF | 1 | R18C22[3][B] | svo_hdmi_inst/svo_tcard/txtmode0/color_index_mode0_1_s29/F
28.902 | 0.821 | tNET | FF | 1 | R18C24[0][A] | svo_hdmi_inst/svo_tcard/txtmode0/color_index_mode0_1_s26/I1
29.528 | 0.626 | tINS | FF | 2 | R18C24[0][A] | svo_hdmi_inst/svo_tcard/txtmode0/color_index_mode0_1_s26/F
29.539 | 0.011 | tNET | FF | 1 | R18C24[1][A] | svo_hdmi_inst/svo_tcard/bramrdaddr_15_s2/I0
30.165 | 0.626 | tINS | FF | 15 | R18C24[1][A] | svo_hdmi_inst/svo_tcard/bramrdaddr_15_s2/F
31.974 | 1.809 | tNET | FF | 1 | R15C23[3][B] | svo_hdmi_inst/svo_tcard/bramrdaddr_12_s0/I3
33.073 | 1.099 | tINS | FF | 11 | R15C23[3][B] | svo_hdmi_inst/svo_tcard/bramrdaddr_12_s0/F
36.346 | 3.273 | tNET | FF | 1 | R9C21[3][A] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_14/I0
36.972 | 0.626 | tINS | FF | 2 | R9C21[3][A] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_14/F
39.074 | 2.103 | tNET | FF | 1 | R9C8[3][A] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELB_dpb_inst_12/I0
40.135 | 1.061 | tINS | FR | 1 | R9C8[3][A] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELB_dpb_inst_12/F
40.927 | 0.791 | tNET | RR | 1 | BSRAM_R10[1] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12/CEB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
39.682 | 39.682 |  |  |  |  | active clock edge time
39.682 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
40.255 | 0.242 | tNET | RR | 1 | BSRAM_R10[1] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12/CLKB
40.068 | -0.187 | tSu |  | 1 | BSRAM_R10[1] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12

Path Statistics:

Clock Skew | -0.015
Setup Relationship | 19.841
Logic Level | 11
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay | cell: 7.737, 37.745%; route: 12.303, 60.019%; tC2Q: 0.458, 2.236%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000%

### Path10

Path Summary:

Slack | -1.151
Data Arrival Time | 22.308
Data Required Time | 21.157
From | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0
To | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_4
Launch Clk | cpuclk:[F]
Latch Clk | svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | 1 | R17C25[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/CLK
14.318 | 0.458 | tC2Q | FF | 16 | R17C25[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q
19.365 | 5.047 | tNET | FF | 1 | R9C21[0][B] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_4/I2
19.991 | 0.626 | tINS | FF | 2 | R9C21[0][B] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_4/F
20.972 | 0.980 | tNET | FF | 1 | R9C14[3][B] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_4/I0
21.597 | 0.625 | tINS | FR | 1 | R9C14[3][B] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_4/F
22.308 | 0.711 | tNET | RR | 1 | BSRAM_R10[3] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_4/CEA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | svo_hdmi_inst/svo_tcard/bram_aclock
20.000 | 0.000 | tCL | RR | 23 | R14C26[0][A] | svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.361 | 1.361 | tNET | RR | 1 | BSRAM_R10[3] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_4/CLKA
21.331 | -0.030 | tUnc |  |  |  |
21.157 | -0.174 | tSu |  | 1 | BSRAM_R10[3] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_4

Path Statistics:

Clock Skew | -2.499
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay | cell: 1.251, 14.809%; route: 6.738, 79.766%; tC2Q: 0.458, 5.425%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.361, 100.000%

### Path11

Path Summary:

Slack | -0.965
Data Arrival Time | 22.122
Data Required Time | 21.157
From | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0
To | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_18
Launch Clk | cpuclk:[F]
Latch Clk | svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | 1 | R17C25[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/CLK
14.318 | 0.458 | tC2Q | FF | 16 | R17C25[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q
16.459 | 2.140 | tNET | FF | 1 | R11C25[3] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_9/I3
17.707 | 1.248 | tINS | FF | 1 | R11C25[3] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_9/F
18.691 | 0.984 | tNET | FF | 1 | R11C22[1][A] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_18/I0
19.717 | 1.026 | tINS | FR | 1 | R11C22[1][A] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_18/F
22.122 | 2.405 | tNET | RR | 1 | BSRAM_R28[3] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_18/CEA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | svo_hdmi_inst/svo_tcard/bram_aclock
20.000 | 0.000 | tCL | RR | 23 | R14C26[0][A] | svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.361 | 1.361 | tNET | RR | 1 | BSRAM_R28[3] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_18/CLKA
21.331 | -0.030 | tUnc |  |  |  |
21.157 | -0.174 | tSu |  | 1 | BSRAM_R28[3] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_18

Path Statistics:

Clock Skew | -2.499
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay | cell: 2.274, 27.524%; route: 5.530, 66.928%; tC2Q: 0.458, 5.548%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.361, 100.000%

### Path12

Path Summary:

Slack | -0.812
Data Arrival Time | 22.099
Data Required Time | 21.288
From | svo_hdmi_inst/svo_tcard/bramwraddr_9_s0
To | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16
Launch Clk | cpuclk:[F]
Latch Clk | svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | 1 | R16C26[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_9_s0/CLK
14.318 | 0.458 | tC2Q | FF | 28 | R16C26[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_9_s0/Q
22.099 | 7.781 | tNET | FF | 1 | BSRAM_R10[0] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16/ADA[11]

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | svo_hdmi_inst/svo_tcard/bram_aclock
20.000 | 0.000 | tCL | RR | 23 | R14C26[0][A] | svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.361 | 1.361 | tNET | RR | 1 | BSRAM_R10[0] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16/CLKA
21.331 | -0.030 | tUnc |  |  |  |
21.288 | -0.043 | tSu |  | 1 | BSRAM_R10[0] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16

Path Statistics:

Clock Skew | -2.499
Setup Relationship | 10.000
Logic Level | 1
Arrival Clock Path Delay | cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.781, 94.437%; tC2Q: 0.458, 5.563%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.361, 100.000%

### Path13

Path Summary:

Slack | -0.394
Data Arrival Time | 40.462
Data Required Time | 40.068
From | svo_hdmi_inst/svo_tcard/grmode1/memcounth_5_s0
To | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_18
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.428 | 0.257 | tNET | FF | 1 | R21C20[0][A] | svo_hdmi_inst/svo_tcard/grmode1/memcounth_5_s0/CLK
20.887 | 0.458 | tC2Q | FF | 5 | R21C20[0][A] | svo_hdmi_inst/svo_tcard/grmode1/memcounth_5_s0/Q
22.532 | 1.645 | tNET | FF | 2 | R18C18[0][A] | svo_hdmi_inst/svo_tcard/grmode1/memrdpos_5_s/I0
23.577 | 1.045 | tINS | FF | 1 | R18C18[0][A] | svo_hdmi_inst/svo_tcard/grmode1/memrdpos_5_s/COUT
23.577 | 0.000 | tNET | FF | 2 | R18C18[0][B] | svo_hdmi_inst/svo_tcard/grmode1/memrdpos_6_s/CIN
23.634 | 0.057 | tINS | FF | 1 | R18C18[0][B] | svo_hdmi_inst/svo_tcard/grmode1/memrdpos_6_s/COUT
23.634 | 0.000 | tNET | FF | 2 | R18C18[1][A] | svo_hdmi_inst/svo_tcard/grmode1/memrdpos_7_s/CIN
23.691 | 0.057 | tINS | FF | 1 | R18C18[1][A] | svo_hdmi_inst/svo_tcard/grmode1/memrdpos_7_s/COUT
23.691 | 0.000 | tNET | FF | 2 | R18C18[1][B] | svo_hdmi_inst/svo_tcard/grmode1/memrdpos_8_s/CIN
23.748 | 0.057 | tINS | FF | 1 | R18C18[1][B] | svo_hdmi_inst/svo_tcard/grmode1/memrdpos_8_s/COUT
23.748 | 0.000 | tNET | FF | 2 | R18C18[2][A] | svo_hdmi_inst/svo_tcard/grmode1/memrdpos_9_s/CIN
24.311 | 0.563 | tINS | FF | 2 | R18C18[2][A] | svo_hdmi_inst/svo_tcard/grmode1/memrdpos_9_s/SUM
26.908 | 2.597 | tNET | FF | 1 | R15C21[3][A] | svo_hdmi_inst/svo_tcard/bramrdaddr_15_s13/I2
28.007 | 1.099 | tINS | FF | 1 | R15C21[3][A] | svo_hdmi_inst/svo_tcard/bramrdaddr_15_s13/F
28.013 | 0.005 | tNET | FF | 1 | R15C21[1][A] | svo_hdmi_inst/svo_tcard/bramrdaddr_15_s11/I2
28.835 | 0.822 | tINS | FF | 1 | R15C21[1][A] | svo_hdmi_inst/svo_tcard/bramrdaddr_15_s11/F
29.171 | 0.336 | tNET | FF | 1 | R15C21[0][B] | svo_hdmi_inst/svo_tcard/bramrdaddr_15_s5/I3
30.270 | 1.099 | tINS | FF | 1 | R15C21[0][B] | svo_hdmi_inst/svo_tcard/bramrdaddr_15_s5/F
30.275 | 0.005 | tNET | FF | 1 | R15C21[2][A] | svo_hdmi_inst/svo_tcard/bramrdaddr_15_s1/I2
31.374 | 1.099 | tINS | FF | 16 | R15C21[2][A] | svo_hdmi_inst/svo_tcard/bramrdaddr_15_s1/F
32.244 | 0.870 | tNET | FF | 1 | R16C23[3][A] | svo_hdmi_inst/svo_tcard/bramrdaddr_11_s0/I0
33.066 | 0.822 | tINS | FF | 19 | R16C23[3][A] | svo_hdmi_inst/svo_tcard/bramrdaddr_11_s0/F
35.537 | 2.471 | tNET | FF | 1 | R11C21[3] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_19/I0
36.718 | 1.181 | tINS | FF | 1 | R11C21[3] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_19/F
37.702 | 0.984 | tNET | FF | 1 | R12C19[1][A] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELB_dpb_inst_18/I0
38.504 | 0.802 | tINS | FR | 1 | R12C19[1][A] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELB_dpb_inst_18/F
40.462 | 1.957 | tNET | RR | 1 | BSRAM_R28[3] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_18/CEB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
39.682 | 39.682 |  |  |  |  | active clock edge time
39.682 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
40.255 | 0.242 | tNET | RR | 1 | BSRAM_R28[3] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_18/CLKB
40.068 | -0.187 | tSu |  | 1 | BSRAM_R28[3] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_18

Path Statistics:

Clock Skew | -0.015
Setup Relationship | 19.841
Logic Level | 10
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay | cell: 8.703, 43.442%; route: 10.872, 54.270%; tC2Q: 0.458, 2.288%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000%

### Path14

Path Summary:

Slack | -0.727
Data Arrival Time | 21.884
Data Required Time | 21.157
From | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0
To | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_17
Launch Clk | cpuclk:[F]
Latch Clk | svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | 1 | R17C25[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/CLK
14.318 | 0.458 | tC2Q | FF | 16 | R17C25[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q
17.585 | 3.267 | tNET | FF | 1 | R11C24[0][B] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_8/I2
18.407 | 0.822 | tINS | FF | 2 | R11C24[0][B] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_8/F
18.418 | 0.011 | tNET | FF | 1 | R11C24[1][B] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_17/I0
19.479 | 1.061 | tINS | FR | 1 | R11C24[1][B] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_17/F
21.884 | 2.405 | tNET | RR | 1 | BSRAM_R28[11] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_17/CEA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | svo_hdmi_inst/svo_tcard/bram_aclock
20.000 | 0.000 | tCL | RR | 23 | R14C26[0][A] | svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.361 | 1.361 | tNET | RR | 1 | BSRAM_R28[11] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_17/CLKA
21.331 | -0.030 | tUnc |  |  |  |
21.157 | -0.174 | tSu |  | 1 | BSRAM_R28[11] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_17

Path Statistics:

Clock Skew | -2.499
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay | cell: 1.883, 23.466%; route: 5.683, 70.822%; tC2Q: 0.458, 5.712%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.361, 100.000%

### Path15

Path Summary:

Slack | -0.664
Data Arrival Time | 21.951
Data Required Time | 21.288
From | svo_hdmi_inst/svo_tcard/bramwraddr_9_s0
To | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_8
Launch Clk | cpuclk:[F]
Latch Clk | svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | 1 | R16C26[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_9_s0/CLK
14.318 | 0.458 | tC2Q | FF | 28 | R16C26[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_9_s0/Q
21.951 | 7.633 | tNET | FF | 1 | BSRAM_R10[2] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_8/ADA[11]

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | svo_hdmi_inst/svo_tcard/bram_aclock
20.000 | 0.000 | tCL | RR | 23 | R14C26[0][A] | svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.361 | 1.361 | tNET | RR | 1 | BSRAM_R10[2] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_8/CLKA
21.331 | -0.030 | tUnc |  |  |  |
21.288 | -0.043 | tSu |  | 1 | BSRAM_R10[2] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_8

Path Statistics:

Clock Skew | -2.499
Setup Relationship | 10.000
Logic Level | 1
Arrival Clock Path Delay | cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.633, 94.335%; tC2Q: 0.458, 5.665%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.361, 100.000%

### Path16

Path Summary:

Slack | -0.654
Data Arrival Time | 21.811
Data Required Time | 21.157
From | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0
To | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16
Launch Clk | cpuclk:[F]
Latch Clk | svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | 1 | R17C25[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/CLK
14.318 | 0.458 | tC2Q | FF | 16 | R17C25[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q
17.585 | 3.267 | tNET | FF | 1 | R11C24[0][B] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_8/I2
18.407 | 0.822 | tINS | FF | 2 | R11C24[0][B] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_8/F
19.387 | 0.980 | tNET | FF | 1 | R11C20[2][B] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_16/I0
20.189 | 0.802 | tINS | FR | 1 | R11C20[2][B] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_16/F
21.811 | 1.622 | tNET | RR | 1 | BSRAM_R10[0] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16/CEA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | svo_hdmi_inst/svo_tcard/bram_aclock
20.000 | 0.000 | tCL | RR | 23 | R14C26[0][A] | svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.361 | 1.361 | tNET | RR | 1 | BSRAM_R10[0] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16/CLKA
21.331 | -0.030 | tUnc |  |  |  |
21.157 | -0.174 | tSu |  | 1 | BSRAM_R10[0] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16

Path Statistics:

Clock Skew | -2.499
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay | cell: 1.624, 20.424%; route: 5.869, 73.812%; tC2Q: 0.458, 5.764%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.361, 100.000%

### Path17

Path Summary:

Slack | -0.621
Data Arrival Time | 21.778
Data Required Time | 21.157
From | svo_hdmi_inst/svo_tcard/bramwraddr_12_s0
To | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_15
Launch Clk | cpuclk:[F]
Latch Clk | svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | 1 | R16C26[2][A] | svo_hdmi_inst/svo_tcard/bramwraddr_12_s0/CLK
14.318 | 0.458 | tC2Q | FF | 18 | R16C26[2][A] | svo_hdmi_inst/svo_tcard/bramwraddr_12_s0/Q
16.610 | 2.292 | tNET | FF | 1 | R15C21[1][B] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_7/I0
17.432 | 0.822 | tINS | FF | 2 | R15C21[1][B] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_7/F
19.210 | 1.778 | tNET | FF | 1 | R18C18[3][B] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_15/I0
20.236 | 1.026 | tINS | FR | 1 | R18C18[3][B] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_15/F
21.778 | 1.542 | tNET | RR | 1 | BSRAM_R28[4] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_15/CEA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | svo_hdmi_inst/svo_tcard/bram_aclock
20.000 | 0.000 | tCL | RR | 23 | R14C26[0][A] | svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.361 | 1.361 | tNET | RR | 1 | BSRAM_R28[4] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_15/CLKA
21.331 | -0.030 | tUnc |  |  |  |
21.157 | -0.174 | tSu |  | 1 | BSRAM_R28[4] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_15

Path Statistics:

Clock Skew | -2.499
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay | cell: 1.848, 23.338%; route: 5.612, 70.874%; tC2Q: 0.458, 5.788%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.361, 100.000%

### Path18

Path Summary:

Slack | -0.569
Data Arrival Time | 21.725
Data Required Time | 21.157
From | svo_hdmi_inst/svo_tcard/bramwraddr_15_s0
To | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_11
Launch Clk | cpuclk:[F]
Latch Clk | svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | 1 | R14C25[1][B] | svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/CLK
14.318 | 0.458 | tC2Q | FF | 16 | R14C25[1][B] | svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/Q
17.573 | 3.254 | tNET | FF | 1 | R17C21[3][B] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_3/I3
18.199 | 0.626 | tINS | FF | 2 | R17C21[3][B] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_3/F
19.493 | 1.294 | tNET | FF | 1 | R18C18[3][A] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_11/I0
20.519 | 1.026 | tINS | FR | 1 | R18C18[3][A] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_11/F
21.725 | 1.206 | tNET | RR | 1 | BSRAM_R28[5] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_11/CEA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | svo_hdmi_inst/svo_tcard/bram_aclock
20.000 | 0.000 | tCL | RR | 23 | R14C26[0][A] | svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.361 | 1.361 | tNET | RR | 1 | BSRAM_R28[5] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_11/CLKA
21.331 | -0.030 | tUnc |  |  |  |
21.157 | -0.174 | tSu |  | 1 | BSRAM_R28[5] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_11

Path Statistics:

Clock Skew | -2.499
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay | cell: 1.652, 21.003%; route: 5.755, 73.170%; tC2Q: 0.458, 5.827%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.361, 100.000%

### Path19

Path Summary:

Slack | -0.560
Data Arrival Time | 21.717
Data Required Time | 21.157
From | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0
To | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_8
Launch Clk | cpuclk:[F]
Latch Clk | svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | 1 | R17C25[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/CLK
14.318 | 0.458 | tC2Q | FF | 16 | R17C25[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q
18.881 | 4.562 | tNET | FF | 1 | R9C22[1][A] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_0/I2
19.507 | 0.626 | tINS | FF | 2 | R9C22[1][A] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_0/F
19.518 | 0.011 | tNET | FF | 1 | R9C22[3][A] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_8/I0
20.143 | 0.625 | tINS | FR | 1 | R9C22[3][A] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_8/F
21.717 | 1.574 | tNET | RR | 1 | BSRAM_R10[2] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_8/CEA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | svo_hdmi_inst/svo_tcard/bram_aclock
20.000 | 0.000 | tCL | RR | 23 | R14C26[0][A] | svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.361 | 1.361 | tNET | RR | 1 | BSRAM_R10[2] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_8/CLKA
21.331 | -0.030 | tUnc |  |  |  |
21.157 | -0.174 | tSu |  | 1 | BSRAM_R10[2] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_8

Path Statistics:

Clock Skew | -2.499
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay | cell: 1.251, 15.922%; route: 6.148, 78.244%; tC2Q: 0.458, 5.834%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.361, 100.000%

### Path20

Path Summary:

Slack | -0.497
Data Arrival Time | 21.785
Data Required Time | 21.288
From | svo_hdmi_inst/svo_tcard/bramwraddr_9_s0
To | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12
Launch Clk | cpuclk:[F]
Latch Clk | svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | 1 | R16C26[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_9_s0/CLK
14.318 | 0.458 | tC2Q | FF | 28 | R16C26[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_9_s0/Q
21.785 | 7.467 | tNET | FF | 1 | BSRAM_R10[1] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12/ADA[11]

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | svo_hdmi_inst/svo_tcard/bram_aclock
20.000 | 0.000 | tCL | RR | 23 | R14C26[0][A] | svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.361 | 1.361 | tNET | RR | 1 | BSRAM_R10[1] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12/CLKA
21.331 | -0.030 | tUnc |  |  |  |
21.288 | -0.043 | tSu |  | 1 | BSRAM_R10[1] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12

Path Statistics:

Clock Skew | -2.499
Setup Relationship | 10.000
Logic Level | 1
Arrival Clock Path Delay | cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.467, 94.217%; tC2Q: 0.458, 5.783%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.361, 100.000%

### Path21

Path Summary:

Slack | -0.283
Data Arrival Time | 21.440
Data Required Time | 21.157
From | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0
To | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_0
Launch Clk | cpuclk:[F]
Latch Clk | svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | 1 | R17C25[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/CLK
14.318 | 0.458 | tC2Q | FF | 16 | R17C25[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q
18.881 | 4.562 | tNET | FF | 1 | R9C22[1][A] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_0/I2
19.506 | 0.625 | tINS | FR | 2 | R9C22[1][A] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_0/F
19.927 | 0.421 | tNET | RR | 1 | R9C23[3][B] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_0/I0
20.729 | 0.802 | tINS | RR | 1 | R9C23[3][B] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_0/F
21.440 | 0.711 | tNET | RR | 1 | BSRAM_R10[6] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_0/CEA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | svo_hdmi_inst/svo_tcard/bram_aclock
20.000 | 0.000 | tCL | RR | 23 | R14C26[0][A] | svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.361 | 1.361 | tNET | RR | 1 | BSRAM_R10[6] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_0/CLKA
21.331 | -0.030 | tUnc |  |  |  |
21.157 | -0.174 | tSu |  | 1 | BSRAM_R10[6] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_0

Path Statistics:

Clock Skew | -2.499
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay | cell: 1.427, 18.826%; route: 5.695, 75.127%; tC2Q: 0.458, 6.047%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.361, 100.000%

### Path22

Path Summary:

Slack | -0.261
Data Arrival Time | 21.418
Data Required Time | 21.157
From | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0
To | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_9
Launch Clk | cpuclk:[F]
Latch Clk | svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | 1 | R17C25[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/CLK
14.318 | 0.458 | tC2Q | FF | 16 | R17C25[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q
17.585 | 3.267 | tNET | FF | 1 | R11C24[1][A] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_1/I2
18.407 | 0.822 | tINS | FF | 2 | R11C24[1][A] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_1/F
18.418 | 0.011 | tNET | FF | 1 | R11C24[0][A] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_9/I0
19.043 | 0.625 | tINS | FR | 1 | R11C24[0][A] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_9/F
21.418 | 2.374 | tNET | RR | 1 | BSRAM_R28[9] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_9/CEA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | svo_hdmi_inst/svo_tcard/bram_aclock
20.000 | 0.000 | tCL | RR | 23 | R14C26[0][A] | svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.361 | 1.361 | tNET | RR | 1 | BSRAM_R28[9] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_9/CLKA
21.331 | -0.030 | tUnc |  |  |  |
21.157 | -0.174 | tSu |  | 1 | BSRAM_R28[9] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_9

Path Statistics:

Clock Skew | -2.499
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay | cell: 1.447, 19.146%; route: 5.653, 74.790%; tC2Q: 0.458, 6.064%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.361, 100.000%

### Path23

Path Summary:

Slack | -0.215
Data Arrival Time | 21.372
Data Required Time | 21.157
From | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0
To | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_14
Launch Clk | cpuclk:[F]
Latch Clk | svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | 1 | R17C25[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/CLK
14.318 | 0.458 | tC2Q | FF | 16 | R17C25[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q
17.916 | 3.598 | tNET | FF | 1 | R11C24[2][A] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_6/I2
18.942 | 1.026 | tINS | FR | 2 | R11C24[2][A] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_6/F
19.365 | 0.423 | tNET | RR | 1 | R11C25[0][A] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_14/I0
20.167 | 0.802 | tINS | RR | 1 | R11C25[0][A] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_14/F
21.372 | 1.205 | tNET | RR | 1 | BSRAM_R10[10] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_14/CEA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | svo_hdmi_inst/svo_tcard/bram_aclock
20.000 | 0.000 | tCL | RR | 23 | R14C26[0][A] | svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.361 | 1.361 | tNET | RR | 1 | BSRAM_R10[10] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_14/CLKA
21.331 | -0.030 | tUnc |  |  |  |
21.157 | -0.174 | tSu |  | 1 | BSRAM_R10[10] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_14

Path Statistics:

Clock Skew | -2.499
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay | cell: 1.828, 24.334%; route: 5.226, 69.564%; tC2Q: 0.458, 6.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.361, 100.000%

### Path24

Path Summary:

Slack | -0.209
Data Arrival Time | 21.366
Data Required Time | 21.157
From | svo_hdmi_inst/svo_tcard/bramwraddr_15_s0
To | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_3
Launch Clk | cpuclk:[F]
Latch Clk | svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | 1 | R14C25[1][B] | svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/CLK
14.318 | 0.458 | tC2Q | FF | 16 | R14C25[1][B] | svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/Q
17.573 | 3.254 | tNET | FF | 1 | R17C21[3][B] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_3/I3
18.199 | 0.626 | tINS | FF | 2 | R17C21[3][B] | svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_3/F
19.179 | 0.980 | tNET | FF | 1 | R18C23[2][A] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_3/I0
20.240 | 1.061 | tINS | FR | 1 | R18C23[2][A] | svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_3/F
21.366 | 1.127 | tNET | RR | 1 | BSRAM_R28[7] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_3/CEA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | svo_hdmi_inst/svo_tcard/bram_aclock
20.000 | 0.000 | tCL | RR | 23 | R14C26[0][A] | svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.361 | 1.361 | tNET | RR | 1 | BSRAM_R28[7] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_3/CLKA
21.331 | -0.030 | tUnc |  |  |  |
21.157 | -0.174 | tSu |  | 1 | BSRAM_R28[7] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_3

Path Statistics:

Clock Skew | -2.499
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay | cell: 1.687, 22.474%; route: 5.361, 71.420%; tC2Q: 0.458, 6.106%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.361, 100.000%

### Path25

Path Summary:

Slack | -0.192
Data Arrival Time | 21.480
Data Required Time | 21.288
From | svo_hdmi_inst/svo_tcard/bramwraddr_0_s0
To | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16
Launch Clk | cpuclk:[F]
Latch Clk | svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | 1 | R15C24[1][B] | svo_hdmi_inst/svo_tcard/bramwraddr_0_s0/CLK
14.318 | 0.458 | tC2Q | FF | 28 | R15C24[1][B] | svo_hdmi_inst/svo_tcard/bramwraddr_0_s0/Q
21.480 | 7.162 | tNET | FF | 1 | BSRAM_R10[0] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16/ADA[2]

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | svo_hdmi_inst/svo_tcard/bram_aclock
20.000 | 0.000 | tCL | RR | 23 | R14C26[0][A] | svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.361 | 1.361 | tNET | RR | 1 | BSRAM_R10[0] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16/CLKA
21.331 | -0.030 | tUnc |  |  |  |
21.288 | -0.043 | tSu |  | 1 | BSRAM_R10[0] | svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16

Path Statistics:

Clock Skew | -2.499
Setup Relationship | 10.000
Logic Level | 1
Arrival Clock Path Delay | cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.162, 93.985%; tC2Q: 0.458, 6.015%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.361, 100.000%

### Hold Analysis Report

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.052
Data Arrival Time | 2.491
Data Required Time | 2.440
From | test1/wng1/lfsr1/sfr_1_s0
To | test1/wng1/noiseout_s0
Launch Clk | test1/wng1/fsr_clk:[R]
Latch Clk | cpuclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | test1/wng1/fsr_clk
0.000 | 0.000 | tCL | RR | 16 | R15C17[1][A] | test1/wng1/fsr_clk_s0/Q
0.966 | 0.966 | tNET | RR | 1 | R13C18[1][B] | test1/wng1/lfsr1/sfr_1_s0/CLK
1.299 | 0.333 | tC2Q | RR | 2 | R13C18[1][B] | test1/wng1/lfsr1/sfr_1_s0/Q
2.491 | 1.192 | tNET | RR | 1 | R15C17[2][A] | test1/wng1/noiseout_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
1.392 | 1.392 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
2.410 | 1.018 | tNET | RR | 1 | R15C17[2][A] | test1/wng1/noiseout_s0/CLK
2.440 | 0.030 | tUnc |  |  |  |
2.440 | 0.000 | tHld |  | 1 | R15C17[2][A] | test1/wng1/noiseout_s0

Path Statistics:

Clock Skew | 1.444
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.966, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.192, 78.148%; tC2Q: 0.333, 21.852%
Required Clock Path Delay | cell: 1.392, 57.770%; route: 1.018, 42.230%

### Path2

Path Summary:

Slack | 0.555
Data Arrival Time | 1.081
Data Required Time | 0.526
From | svo_hdmi_inst/svo_tmds_1/dout_9_s0
To | svo_hdmi_inst/tmds_serdes[1]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | R2C39[0][B] | svo_hdmi_inst/svo_tmds_1/dout_9_s0/CLK
0.846 | 0.333 | tC2Q | RF | 2 | R2C39[0][B] | svo_hdmi_inst/svo_tmds_1/dout_9_s0/Q
1.081 | 0.234 | tNET | FF | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]/D9

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]/PCLK
0.526 | 0.012 | tHld |  | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.234, 41.295%; tC2Q: 0.333, 58.705%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%

### Path3

Path Summary:

Slack | 0.555
Data Arrival Time | 1.081
Data Required Time | 0.526
From | svo_hdmi_inst/svo_tmds_1/dout_9_s0
To | svo_hdmi_inst/tmds_serdes[1]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | R2C39[0][B] | svo_hdmi_inst/svo_tmds_1/dout_9_s0/CLK
0.846 | 0.333 | tC2Q | RF | 2 | R2C39[0][B] | svo_hdmi_inst/svo_tmds_1/dout_9_s0/Q
1.081 | 0.234 | tNET | FF | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]/D2

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]/PCLK
0.526 | 0.012 | tHld |  | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.234, 41.295%; tC2Q: 0.333, 58.705%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%

### Path4

Path Summary:

Slack | 0.559
Data Arrival Time | 1.085
Data Required Time | 0.526
From | svo_hdmi_inst/svo_tmds_2/dout_3_s0
To | svo_hdmi_inst/tmds_serdes[2]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | R2C38[0][A] | svo_hdmi_inst/svo_tmds_2/dout_3_s0/CLK
0.846 | 0.333 | tC2Q | RF | 2 | R2C38[0][A] | svo_hdmi_inst/svo_tmds_2/dout_3_s0/Q
1.085 | 0.238 | tNET | FF | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]/D3

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]/PCLK
0.526 | 0.012 | tHld |  | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.238, 41.685%; tC2Q: 0.333, 58.315%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%

### Path5

Path Summary:

Slack | 0.559
Data Arrival Time | 1.085
Data Required Time | 0.526
From | svo_hdmi_inst/svo_tmds_2/dout_3_s0
To | svo_hdmi_inst/tmds_serdes[2]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | R2C38[0][A] | svo_hdmi_inst/svo_tmds_2/dout_3_s0/CLK
0.846 | 0.333 | tC2Q | RF | 2 | R2C38[0][A] | svo_hdmi_inst/svo_tmds_2/dout_3_s0/Q
1.085 | 0.238 | tNET | FF | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]/D1

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]/PCLK
0.526 | 0.012 | tHld |  | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.238, 41.685%; tC2Q: 0.333, 58.315%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%

### Path6

Path Summary:

Slack | 0.708
Data Arrival Time | 21.070
Data Required Time | 20.362
From | svo_hdmi_inst/svo_tcard/grmode1/prescnibble_0_s1
To | svo_hdmi_inst/svo_tcard/grmode1/prescnibble_0_s1
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.362 | 0.191 | tNET | FF | 1 | R18C25[0][A] | svo_hdmi_inst/svo_tcard/grmode1/prescnibble_0_s1/CLK
20.696 | 0.333 | tC2Q | FR | 2 | R18C25[0][A] | svo_hdmi_inst/svo_tcard/grmode1/prescnibble_0_s1/Q
20.698 | 0.002 | tNET | RR | 1 | R18C25[0][A] | svo_hdmi_inst/svo_tcard/grmode1/n68_s3/I3
21.070 | 0.372 | tINS | RF | 1 | R18C25[0][A] | svo_hdmi_inst/svo_tcard/grmode1/n68_s3/F
21.070 | 0.000 | tNET | FF | 1 | R18C25[0][A] | svo_hdmi_inst/svo_tcard/grmode1/prescnibble_0_s1/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.362 | 0.191 | tNET | FF | 1 | R18C25[0][A] | svo_hdmi_inst/svo_tcard/grmode1/prescnibble_0_s1/CLK
20.362 | 0.000 | tHld |  | 1 | R18C25[0][A] | svo_hdmi_inst/svo_tcard/grmode1/prescnibble_0_s1

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000%

### Path7

Path Summary:

Slack | 0.708
Data Arrival Time | 21.070
Data Required Time | 20.362
From | svo_hdmi_inst/svo_tcard/grmode1/prescnibble_1_s0
To | svo_hdmi_inst/svo_tcard/grmode1/prescnibble_1_s0
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.362 | 0.191 | tNET | FF | 1 | R18C25[1][A] | svo_hdmi_inst/svo_tcard/grmode1/prescnibble_1_s0/CLK
20.696 | 0.333 | tC2Q | FR | 5 | R18C25[1][A] | svo_hdmi_inst/svo_tcard/grmode1/prescnibble_1_s0/Q
20.698 | 0.002 | tNET | RR | 1 | R18C25[1][A] | svo_hdmi_inst/svo_tcard/grmode1/n67_s3/I0
21.070 | 0.372 | tINS | RF | 1 | R18C25[1][A] | svo_hdmi_inst/svo_tcard/grmode1/n67_s3/F
21.070 | 0.000 | tNET | FF | 1 | R18C25[1][A] | svo_hdmi_inst/svo_tcard/grmode1/prescnibble_1_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.362 | 0.191 | tNET | FF | 1 | R18C25[1][A] | svo_hdmi_inst/svo_tcard/grmode1/prescnibble_1_s0/CLK
20.362 | 0.000 | tHld |  | 1 | R18C25[1][A] | svo_hdmi_inst/svo_tcard/grmode1/prescnibble_1_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000%

### Path8

Path Summary:

Slack | 0.708
Data Arrival Time | 21.070
Data Required Time | 20.362
From | svo_hdmi_inst/svo_tcard/grmode1/prescl_1_s0
To | svo_hdmi_inst/svo_tcard/grmode1/prescl_1_s0
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.362 | 0.191 | tNET | FF | 1 | R22C22[0][A] | svo_hdmi_inst/svo_tcard/grmode1/prescl_1_s0/CLK
20.696 | 0.333 | tC2Q | FR | 2 | R22C22[0][A] | svo_hdmi_inst/svo_tcard/grmode1/prescl_1_s0/Q
20.698 | 0.002 | tNET | RR | 1 | R22C22[0][A] | svo_hdmi_inst/svo_tcard/grmode1/n199_s2/I2
21.070 | 0.372 | tINS | RF | 1 | R22C22[0][A] | svo_hdmi_inst/svo_tcard/grmode1/n199_s2/F
21.070 | 0.000 | tNET | FF | 1 | R22C22[0][A] | svo_hdmi_inst/svo_tcard/grmode1/prescl_1_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.362 | 0.191 | tNET | FF | 1 | R22C22[0][A] | svo_hdmi_inst/svo_tcard/grmode1/prescl_1_s0/CLK
20.362 | 0.000 | tHld |  | 1 | R22C22[0][A] | svo_hdmi_inst/svo_tcard/grmode1/prescl_1_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000%

### Path9

Path Summary:

Slack | 0.708
Data Arrival Time | 21.070
Data Required Time | 20.362
From | svo_hdmi_inst/svo_tcard/grmode1/memcountl_4_s0
To | svo_hdmi_inst/svo_tcard/grmode1/memcountl_4_s0
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.362 | 0.191 | tNET | FF | 1 | R21C22[1][A] | svo_hdmi_inst/svo_tcard/grmode1/memcountl_4_s0/CLK
20.696 | 0.333 | tC2Q | FR | 4 | R21C22[1][A] | svo_hdmi_inst/svo_tcard/grmode1/memcountl_4_s0/Q
20.698 | 0.002 | tNET | RR | 1 | R21C22[1][A] | svo_hdmi_inst/svo_tcard/grmode1/n132_s2/I1
21.070 | 0.372 | tINS | RF | 1 | R21C22[1][A] | svo_hdmi_inst/svo_tcard/grmode1/n132_s2/F
21.070 | 0.000 | tNET | FF | 1 | R21C22[1][A] | svo_hdmi_inst/svo_tcard/grmode1/memcountl_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.362 | 0.191 | tNET | FF | 1 | R21C22[1][A] | svo_hdmi_inst/svo_tcard/grmode1/memcountl_4_s0/CLK
20.362 | 0.000 | tHld |  | 1 | R21C22[1][A] | svo_hdmi_inst/svo_tcard/grmode1/memcountl_4_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000%

### Path10

Path Summary:

Slack | 0.708
Data Arrival Time | 21.070
Data Required Time | 20.362
From | svo_hdmi_inst/svo_tcard/grmode1/memcounth_5_s0
To | svo_hdmi_inst/svo_tcard/grmode1/memcounth_5_s0
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.362 | 0.191 | tNET | FF | 1 | R21C20[0][A] | svo_hdmi_inst/svo_tcard/grmode1/memcounth_5_s0/CLK
20.696 | 0.333 | tC2Q | FR | 5 | R21C20[0][A] | svo_hdmi_inst/svo_tcard/grmode1/memcounth_5_s0/Q
20.698 | 0.002 | tNET | RR | 1 | R21C20[0][A] | svo_hdmi_inst/svo_tcard/grmode1/n148_s3/I0
21.070 | 0.372 | tINS | RF | 1 | R21C20[0][A] | svo_hdmi_inst/svo_tcard/grmode1/n148_s3/F
21.070 | 0.000 | tNET | FF | 1 | R21C20[0][A] | svo_hdmi_inst/svo_tcard/grmode1/memcounth_5_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.362 | 0.191 | tNET | FF | 1 | R21C20[0][A] | svo_hdmi_inst/svo_tcard/grmode1/memcounth_5_s0/CLK
20.362 | 0.000 | tHld |  | 1 | R21C20[0][A] | svo_hdmi_inst/svo_tcard/grmode1/memcounth_5_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000%

### Path11

Path Summary:

Slack | 0.708
Data Arrival Time | 21.070
Data Required Time | 20.362
From | svo_hdmi_inst/svo_tcard/txtmode0/memlinebase_8_s0
To | svo_hdmi_inst/svo_tcard/txtmode0/memlinebase_8_s0
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.362 | 0.191 | tNET | FF | 1 | R22C23[1][A] | svo_hdmi_inst/svo_tcard/txtmode0/memlinebase_8_s0/CLK
20.696 | 0.333 | tC2Q | FR | 6 | R22C23[1][A] | svo_hdmi_inst/svo_tcard/txtmode0/memlinebase_8_s0/Q
20.698 | 0.002 | tNET | RR | 1 | R22C23[1][A] | svo_hdmi_inst/svo_tcard/txtmode0/n172_s0/I1
21.070 | 0.372 | tINS | RF | 1 | R22C23[1][A] | svo_hdmi_inst/svo_tcard/txtmode0/n172_s0/F
21.070 | 0.000 | tNET | FF | 1 | R22C23[1][A] | svo_hdmi_inst/svo_tcard/txtmode0/memlinebase_8_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.362 | 0.191 | tNET | FF | 1 | R22C23[1][A] | svo_hdmi_inst/svo_tcard/txtmode0/memlinebase_8_s0/CLK
20.362 | 0.000 | tHld |  | 1 | R22C23[1][A] | svo_hdmi_inst/svo_tcard/txtmode0/memlinebase_8_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000%

### Path12

Path Summary:

Slack | 0.708
Data Arrival Time | 21.070
Data Required Time | 20.362
From | svo_hdmi_inst/svo_tcard/pixelcount_1_s1
To | svo_hdmi_inst/svo_tcard/pixelcount_1_s1
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.362 | 0.191 | tNET | FF | 1 | R22C26[0][A] | svo_hdmi_inst/svo_tcard/pixelcount_1_s1/CLK
20.696 | 0.333 | tC2Q | FR | 5 | R22C26[0][A] | svo_hdmi_inst/svo_tcard/pixelcount_1_s1/Q
20.698 | 0.002 | tNET | RR | 1 | R22C26[0][A] | svo_hdmi_inst/svo_tcard/n1695_s4/I3
21.070 | 0.372 | tINS | RF | 1 | R22C26[0][A] | svo_hdmi_inst/svo_tcard/n1695_s4/F
21.070 | 0.000 | tNET | FF | 1 | R22C26[0][A] | svo_hdmi_inst/svo_tcard/pixelcount_1_s1/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.362 | 0.191 | tNET | FF | 1 | R22C26[0][A] | svo_hdmi_inst/svo_tcard/pixelcount_1_s1/CLK
20.362 | 0.000 | tHld |  | 1 | R22C26[0][A] | svo_hdmi_inst/svo_tcard/pixelcount_1_s1

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000%

### Path13

Path Summary:

Slack | 0.708
Data Arrival Time | 21.070
Data Required Time | 20.362
From | svo_hdmi_inst/svo_tcard/pixelcount_8_s0
To | svo_hdmi_inst/svo_tcard/pixelcount_8_s0
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.362 | 0.191 | tNET | FF | 1 | R23C26[1][A] | svo_hdmi_inst/svo_tcard/pixelcount_8_s0/CLK
20.696 | 0.333 | tC2Q | FR | 5 | R23C26[1][A] | svo_hdmi_inst/svo_tcard/pixelcount_8_s0/Q
20.698 | 0.002 | tNET | RR | 1 | R23C26[1][A] | svo_hdmi_inst/svo_tcard/n1688_s2/I2
21.070 | 0.372 | tINS | RF | 1 | R23C26[1][A] | svo_hdmi_inst/svo_tcard/n1688_s2/F
21.070 | 0.000 | tNET | FF | 1 | R23C26[1][A] | svo_hdmi_inst/svo_tcard/pixelcount_8_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.362 | 0.191 | tNET | FF | 1 | R23C26[1][A] | svo_hdmi_inst/svo_tcard/pixelcount_8_s0/CLK
20.362 | 0.000 | tHld |  | 1 | R23C26[1][A] | svo_hdmi_inst/svo_tcard/pixelcount_8_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000%

### Path14

Path Summary:

Slack | 0.708
Data Arrival Time | 21.070
Data Required Time | 20.362
From | svo_hdmi_inst/svo_tcard/pixelcount_14_s0
To | svo_hdmi_inst/svo_tcard/pixelcount_14_s0
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.362 | 0.191 | tNET | FF | 1 | R22C24[0][A] | svo_hdmi_inst/svo_tcard/pixelcount_14_s0/CLK
20.696 | 0.333 | tC2Q | FR | 3 | R22C24[0][A] | svo_hdmi_inst/svo_tcard/pixelcount_14_s0/Q
20.698 | 0.002 | tNET | RR | 1 | R22C24[0][A] | svo_hdmi_inst/svo_tcard/n1682_s2/I3
21.070 | 0.372 | tINS | RF | 1 | R22C24[0][A] | svo_hdmi_inst/svo_tcard/n1682_s2/F
21.070 | 0.000 | tNET | FF | 1 | R22C24[0][A] | svo_hdmi_inst/svo_tcard/pixelcount_14_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
19.841 | 19.841 |  |  |  |  | active clock edge time
19.841 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171 | 0.330 | tCL | FF | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
20.362 | 0.191 | tNET | FF | 1 | R22C24[0][A] | svo_hdmi_inst/svo_tcard/pixelcount_14_s0/CLK
20.362 | 0.000 | tHld |  | 1 | R22C24[0][A] | svo_hdmi_inst/svo_tcard/pixelcount_14_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000%

### Path15

Path Summary:

Slack | 0.708
Data Arrival Time | 13.382
Data Required Time | 12.675
From | svo_hdmi_inst/svo_tcard/cled3_0_s3
To | svo_hdmi_inst/svo_tcard/cled3_0_s3
Launch Clk | cpuclk:[F]
Latch Clk | cpuclk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
11.542 | 1.542 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
12.675 | 1.133 | tNET | FF | 1 | R6C28[0][A] | svo_hdmi_inst/svo_tcard/cled3_0_s3/CLK
13.008 | 0.333 | tC2Q | FR | 3 | R6C28[0][A] | svo_hdmi_inst/svo_tcard/cled3_0_s3/Q
13.010 | 0.002 | tNET | RR | 1 | R6C28[0][A] | svo_hdmi_inst/svo_tcard/n266_s3/I2
13.382 | 0.372 | tINS | RF | 1 | R6C28[0][A] | svo_hdmi_inst/svo_tcard/n266_s3/F
13.382 | 0.000 | tNET | FF | 1 | R6C28[0][A] | svo_hdmi_inst/svo_tcard/cled3_0_s3/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
11.542 | 1.542 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
12.675 | 1.133 | tNET | FF | 1 | R6C28[0][A] | svo_hdmi_inst/svo_tcard/cled3_0_s3/CLK
12.675 | 0.000 | tHld |  | 1 | R6C28[0][A] | svo_hdmi_inst/svo_tcard/cled3_0_s3

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.542, 57.649%; route: 1.133, 42.351%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.542, 57.649%; route: 1.133, 42.351%

### Path16

Path Summary:

Slack | 0.708
Data Arrival Time | 13.382
Data Required Time | 12.675
From | svo_hdmi_inst/svo_tcard/bramwraddr_6_s0
To | svo_hdmi_inst/svo_tcard/bramwraddr_6_s0
Launch Clk | cpuclk:[F]
Latch Clk | cpuclk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
11.542 | 1.542 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
12.675 | 1.133 | tNET | FF | 1 | R16C20[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_6_s0/CLK
13.008 | 0.333 | tC2Q | FR | 25 | R16C20[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_6_s0/Q
13.010 | 0.002 | tNET | RR | 1 | R16C20[1][A] | svo_hdmi_inst/svo_tcard/n1106_s0/I3
13.382 | 0.372 | tINS | RF | 1 | R16C20[1][A] | svo_hdmi_inst/svo_tcard/n1106_s0/F
13.382 | 0.000 | tNET | FF | 1 | R16C20[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_6_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
11.542 | 1.542 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
12.675 | 1.133 | tNET | FF | 1 | R16C20[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_6_s0/CLK
12.675 | 0.000 | tHld |  | 1 | R16C20[1][A] | svo_hdmi_inst/svo_tcard/bramwraddr_6_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.542, 57.649%; route: 1.133, 42.351%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.542, 57.649%; route: 1.133, 42.351%

### Path17

Path Summary:

Slack | 0.708
Data Arrival Time | 13.382
Data Required Time | 12.675
From | svo_hdmi_inst/svo_tcard/counter_0_s0
To | svo_hdmi_inst/svo_tcard/counter_0_s0
Launch Clk | cpuclk:[F]
Latch Clk | cpuclk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
11.542 | 1.542 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
12.675 | 1.133 | tNET | FF | 1 | R7C18[0][A] | svo_hdmi_inst/svo_tcard/counter_0_s0/CLK
13.008 | 0.333 | tC2Q | FR | 2 | R7C18[0][A] | svo_hdmi_inst/svo_tcard/counter_0_s0/Q
13.010 | 0.002 | tNET | RR | 1 | R7C18[0][A] | svo_hdmi_inst/svo_tcard/n98_s2/I0
13.382 | 0.372 | tINS | RF | 1 | R7C18[0][A] | svo_hdmi_inst/svo_tcard/n98_s2/F
13.382 | 0.000 | tNET | FF | 1 | R7C18[0][A] | svo_hdmi_inst/svo_tcard/counter_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | cpuclk
10.000 | 0.000 | tCL | FF | 1 | IOB23[A] | cpuclk_ibuf/I
11.542 | 1.542 | tINS | FF | 563 | IOB23[A] | cpuclk_ibuf/O
12.675 | 1.133 | tNET | FF | 1 | R7C18[0][A] | svo_hdmi_inst/svo_tcard/counter_0_s0/CLK
12.675 | 0.000 | tHld |  | 1 | R7C18[0][A] | svo_hdmi_inst/svo_tcard/counter_0_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.542, 57.649%; route: 1.133, 42.351%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.542, 57.649%; route: 1.133, 42.351%

### Path18

Path Summary:

Slack | 0.708
Data Arrival Time | 3.117
Data Required Time | 2.410
From | ps2_1/bitsreceived_2_s0
To | ps2_1/bitsreceived_2_s0
Launch Clk | cpuclk:[R]
Latch Clk | cpuclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
1.392 | 1.392 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
2.410 | 1.018 | tNET | RR | 1 | R11C7[0][A] | ps2_1/bitsreceived_2_s0/CLK
2.743 | 0.333 | tC2Q | RR | 3 | R11C7[0][A] | ps2_1/bitsreceived_2_s0/Q
2.745 | 0.002 | tNET | RR | 1 | R11C7[0][A] | ps2_1/n106_s1/I2
3.117 | 0.372 | tINS | RF | 1 | R11C7[0][A] | ps2_1/n106_s1/F
3.117 | 0.000 | tNET | FF | 1 | R11C7[0][A] | ps2_1/bitsreceived_2_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
1.392 | 1.392 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
2.410 | 1.018 | tNET | RR | 1 | R11C7[0][A] | ps2_1/bitsreceived_2_s0/CLK
2.410 | 0.000 | tHld |  | 1 | R11C7[0][A] | ps2_1/bitsreceived_2_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 57.770%; route: 1.018, 42.230%

### Path19

Path Summary:

Slack | 0.708
Data Arrival Time | 3.117
Data Required Time | 2.410
From | ps2_1/bitsreceived_3_s0
To | ps2_1/bitsreceived_3_s0
Launch Clk | cpuclk:[R]
Latch Clk | cpuclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
1.392 | 1.392 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
2.410 | 1.018 | tNET | RR | 1 | R9C7[0][A] | ps2_1/bitsreceived_3_s0/CLK
2.743 | 0.333 | tC2Q | RR | 2 | R9C7[0][A] | ps2_1/bitsreceived_3_s0/Q
2.745 | 0.002 | tNET | RR | 1 | R9C7[0][A] | ps2_1/n105_s3/I1
3.117 | 0.372 | tINS | RF | 1 | R9C7[0][A] | ps2_1/n105_s3/F
3.117 | 0.000 | tNET | FF | 1 | R9C7[0][A] | ps2_1/bitsreceived_3_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
1.392 | 1.392 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
2.410 | 1.018 | tNET | RR | 1 | R9C7[0][A] | ps2_1/bitsreceived_3_s0/CLK
2.410 | 0.000 | tHld |  | 1 | R9C7[0][A] | ps2_1/bitsreceived_3_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 57.770%; route: 1.018, 42.230%

### Path20

Path Summary:

Slack | 0.708
Data Arrival Time | 3.117
Data Required Time | 2.410
From | test1/dac1/state_4_s0
To | test1/dac1/state_4_s0
Launch Clk | cpuclk:[R]
Latch Clk | cpuclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
1.392 | 1.392 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
2.410 | 1.018 | tNET | RR | 1 | R22C18[0][A] | test1/dac1/state_4_s0/CLK
2.743 | 0.333 | tC2Q | RR | 4 | R22C18[0][A] | test1/dac1/state_4_s0/Q
2.745 | 0.002 | tNET | RR | 1 | R22C18[0][A] | test1/dac1/n59_s1/I1
3.117 | 0.372 | tINS | RF | 1 | R22C18[0][A] | test1/dac1/n59_s1/F
3.117 | 0.000 | tNET | FF | 1 | R22C18[0][A] | test1/dac1/state_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
1.392 | 1.392 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
2.410 | 1.018 | tNET | RR | 1 | R22C18[0][A] | test1/dac1/state_4_s0/CLK
2.410 | 0.000 | tHld |  | 1 | R22C18[0][A] | test1/dac1/state_4_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 57.770%; route: 1.018, 42.230%

### Path21

Path Summary:

Slack | 0.708
Data Arrival Time | 3.117
Data Required Time | 2.410
From | test1/wng1/clkdiv_1_s2
To | test1/wng1/clkdiv_1_s2
Launch Clk | cpuclk:[R]
Latch Clk | cpuclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
1.392 | 1.392 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
2.410 | 1.018 | tNET | RR | 1 | R14C18[1][A] | test1/wng1/clkdiv_1_s2/CLK
2.743 | 0.333 | tC2Q | RR | 4 | R14C18[1][A] | test1/wng1/clkdiv_1_s2/Q
2.745 | 0.002 | tNET | RR | 1 | R14C18[1][A] | test1/wng1/n85_s4/I3
3.117 | 0.372 | tINS | RF | 1 | R14C18[1][A] | test1/wng1/n85_s4/F
3.117 | 0.000 | tNET | FF | 1 | R14C18[1][A] | test1/wng1/clkdiv_1_s2/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
1.392 | 1.392 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
2.410 | 1.018 | tNET | RR | 1 | R14C18[1][A] | test1/wng1/clkdiv_1_s2/CLK
2.410 | 0.000 | tHld |  | 1 | R14C18[1][A] | test1/wng1/clkdiv_1_s2

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 57.770%; route: 1.018, 42.230%

### Path22

Path Summary:

Slack | 0.708
Data Arrival Time | 3.117
Data Required Time | 2.410
From | test1/wng1/clkdiv_2_s0
To | test1/wng1/clkdiv_2_s0
Launch Clk | cpuclk:[R]
Latch Clk | cpuclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
1.392 | 1.392 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
2.410 | 1.018 | tNET | RR | 1 | R14C17[1][A] | test1/wng1/clkdiv_2_s0/CLK
2.743 | 0.333 | tC2Q | RR | 4 | R14C17[1][A] | test1/wng1/clkdiv_2_s0/Q
2.745 | 0.002 | tNET | RR | 1 | R14C17[1][A] | test1/wng1/n84_s4/I0
3.117 | 0.372 | tINS | RF | 1 | R14C17[1][A] | test1/wng1/n84_s4/F
3.117 | 0.000 | tNET | FF | 1 | R14C17[1][A] | test1/wng1/clkdiv_2_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
1.392 | 1.392 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
2.410 | 1.018 | tNET | RR | 1 | R14C17[1][A] | test1/wng1/clkdiv_2_s0/CLK
2.410 | 0.000 | tHld |  | 1 | R14C17[1][A] | test1/wng1/clkdiv_2_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 57.770%; route: 1.018, 42.230%

### Path23

Path Summary:

Slack | 0.708
Data Arrival Time | 3.117
Data Required Time | 2.410
From | test1/wng1/clkdiv_4_s0
To | test1/wng1/clkdiv_4_s0
Launch Clk | cpuclk:[R]
Latch Clk | cpuclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
1.392 | 1.392 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
2.410 | 1.018 | tNET | RR | 1 | R14C17[0][A] | test1/wng1/clkdiv_4_s0/CLK
2.743 | 0.333 | tC2Q | RR | 2 | R14C17[0][A] | test1/wng1/clkdiv_4_s0/Q
2.745 | 0.002 | tNET | RR | 1 | R14C17[0][A] | test1/wng1/n82_s2/I3
3.117 | 0.372 | tINS | RF | 1 | R14C17[0][A] | test1/wng1/n82_s2/F
3.117 | 0.000 | tNET | FF | 1 | R14C17[0][A] | test1/wng1/clkdiv_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
1.392 | 1.392 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
2.410 | 1.018 | tNET | RR | 1 | R14C17[0][A] | test1/wng1/clkdiv_4_s0/CLK
2.410 | 0.000 | tHld |  | 1 | R14C17[0][A] | test1/wng1/clkdiv_4_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 57.770%; route: 1.018, 42.230%

### Path24

Path Summary:

Slack | 0.708
Data Arrival Time | 3.117
Data Required Time | 2.410
From | test1/wng1/clkdiv_5_s0
To | test1/wng1/clkdiv_5_s0
Launch Clk | cpuclk:[R]
Latch Clk | cpuclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
1.392 | 1.392 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
2.410 | 1.018 | tNET | RR | 1 | R14C16[0][A] | test1/wng1/clkdiv_5_s0/CLK
2.743 | 0.333 | tC2Q | RR | 4 | R14C16[0][A] | test1/wng1/clkdiv_5_s0/Q
2.745 | 0.002 | tNET | RR | 1 | R14C16[0][A] | test1/wng1/n81_s2/I1
3.117 | 0.372 | tINS | RF | 1 | R14C16[0][A] | test1/wng1/n81_s2/F
3.117 | 0.000 | tNET | FF | 1 | R14C16[0][A] | test1/wng1/clkdiv_5_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
1.392 | 1.392 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
2.410 | 1.018 | tNET | RR | 1 | R14C16[0][A] | test1/wng1/clkdiv_5_s0/CLK
2.410 | 0.000 | tHld |  | 1 | R14C16[0][A] | test1/wng1/clkdiv_5_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 57.770%; route: 1.018, 42.230%

### Path25

Path Summary:

Slack | 0.708
Data Arrival Time | 3.117
Data Required Time | 2.410
From | test1/toneC/clkdiv_3_s0
To | test1/toneC/clkdiv_3_s0
Launch Clk | cpuclk:[R]
Latch Clk | cpuclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
1.392 | 1.392 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
2.410 | 1.018 | tNET | RR | 1 | R14C15[0][A] | test1/toneC/clkdiv_3_s0/CLK
2.743 | 0.333 | tC2Q | RR | 2 | R14C15[0][A] | test1/toneC/clkdiv_3_s0/Q
2.745 | 0.002 | tNET | RR | 1 | R14C15[0][A] | test1/toneC/n111_s2/I3
3.117 | 0.372 | tINS | RF | 1 | R14C15[0][A] | test1/toneC/n111_s2/F
3.117 | 0.000 | tNET | FF | 1 | R14C15[0][A] | test1/toneC/clkdiv_3_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | cpuclk
0.000 | 0.000 | tCL | RR | 1 | IOB23[A] | cpuclk_ibuf/I
1.392 | 1.392 | tINS | RR | 563 | IOB23[A] | cpuclk_ibuf/O
2.410 | 1.018 | tNET | RR | 1 | R14C15[0][A] | test1/toneC/clkdiv_3_s0/CLK
2.410 | 0.000 | tHld |  | 1 | R14C15[0][A] | test1/toneC/clkdiv_3_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 57.770%; route: 1.018, 42.230%

### Recovery Analysis Report

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 1.370
Data Arrival Time | 5.038
Data Required Time | 6.409
From | svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To | svo_hdmi_inst/tmds_serdes[0]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.572 | 0.242 | tNET | RR | 1 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030 | 0.458 | tC2Q | RF | 7 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.374 | 0.343 | tNET | FF | 1 | R15C34[2][A] | svo_hdmi_inst/n147_s1/I1
2.406 | 1.032 | tINS | FF | 96 | R15C34[2][A] | svo_hdmi_inst/n147_s1/F
5.038 | 2.633 | tNET | FF | 1 | IOT41[A] | svo_hdmi_inst/tmds_serdes[0]/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.968 | 3.968 |  |  |  |  | active clock edge time
3.968 | 0.000 |  |  |  |  | u_pll/rpll_inst/CLKOUT.default_gen_clk
6.362 | 2.394 | tCL | FF | 4 | PLL_R | u_pll/rpll_inst/CLKOUT
6.484 | 0.121 | tNET | FF | 1 | IOT41[A] | svo_hdmi_inst/tmds_serdes[0]/FCLK
6.454 | -0.030 | tUnc |  |  |  |
6.409 | -0.045 | tSu |  | 1 | IOT41[A] | svo_hdmi_inst/tmds_serdes[0]

Path Statistics:

Clock Skew | 1.943
Setup Relationship | 3.968
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay | cell: 1.032, 23.107%; route: 2.976, 66.630%; tC2Q: 0.458, 10.262%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.121, 100.000%

### Path2

Path Summary:

Slack | 1.370
Data Arrival Time | 5.038
Data Required Time | 6.409
From | svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To | svo_hdmi_inst/tmds_serdes[1]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.572 | 0.242 | tNET | RR | 1 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030 | 0.458 | tC2Q | RF | 7 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.374 | 0.343 | tNET | FF | 1 | R15C34[2][A] | svo_hdmi_inst/n147_s1/I1
2.406 | 1.032 | tINS | FF | 96 | R15C34[2][A] | svo_hdmi_inst/n147_s1/F
5.038 | 2.633 | tNET | FF | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.968 | 3.968 |  |  |  |  | active clock edge time
3.968 | 0.000 |  |  |  |  | u_pll/rpll_inst/CLKOUT.default_gen_clk
6.362 | 2.394 | tCL | FF | 4 | PLL_R | u_pll/rpll_inst/CLKOUT
6.484 | 0.121 | tNET | FF | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]/FCLK
6.454 | -0.030 | tUnc |  |  |  |
6.409 | -0.045 | tSu |  | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew | 1.943
Setup Relationship | 3.968
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay | cell: 1.032, 23.107%; route: 2.976, 66.630%; tC2Q: 0.458, 10.262%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.121, 100.000%

### Path3

Path Summary:

Slack | 1.370
Data Arrival Time | 5.038
Data Required Time | 6.409
From | svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To | svo_hdmi_inst/tmds_serdes[2]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.572 | 0.242 | tNET | RR | 1 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030 | 0.458 | tC2Q | RF | 7 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.374 | 0.343 | tNET | FF | 1 | R15C34[2][A] | svo_hdmi_inst/n147_s1/I1
2.406 | 1.032 | tINS | FF | 96 | R15C34[2][A] | svo_hdmi_inst/n147_s1/F
5.038 | 2.633 | tNET | FF | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.968 | 3.968 |  |  |  |  | active clock edge time
3.968 | 0.000 |  |  |  |  | u_pll/rpll_inst/CLKOUT.default_gen_clk
6.362 | 2.394 | tCL | FF | 4 | PLL_R | u_pll/rpll_inst/CLKOUT
6.484 | 0.121 | tNET | FF | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]/FCLK
6.454 | -0.030 | tUnc |  |  |  |
6.409 | -0.045 | tSu |  | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew | 1.943
Setup Relationship | 3.968
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay | cell: 1.032, 23.107%; route: 2.976, 66.630%; tC2Q: 0.458, 10.262%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.121, 100.000%

### Path4

Path Summary:

Slack | 5.332
Data Arrival Time | 5.038
Data Required Time | 10.370
From | svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To | svo_hdmi_inst/tmds_serdes[2]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.572 | 0.242 | tNET | RR | 1 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030 | 0.458 | tC2Q | RF | 7 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.374 | 0.343 | tNET | FF | 1 | R15C34[2][A] | svo_hdmi_inst/n147_s1/I1
2.406 | 1.032 | tINS | FF | 96 | R15C34[2][A] | svo_hdmi_inst/n147_s1/F
5.038 | 2.633 | tNET | FF | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
7.936 | 7.936 |  |  |  |  | active clock edge time
7.936 | 0.000 |  |  |  |  | u_pll/rpll_inst/CLKOUT.default_gen_clk
10.330 | 2.394 | tCL | RR | 4 | PLL_R | u_pll/rpll_inst/CLKOUT
10.445 | 0.115 | tNET | RR | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]/FCLK
10.415 | -0.030 | tUnc |  |  |  |
10.370 | -0.045 | tSu |  | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew | 1.937
Setup Relationship | 7.936
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay | cell: 1.032, 23.107%; route: 2.976, 66.630%; tC2Q: 0.458, 10.262%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.115, 100.000%

### Path5

Path Summary:

Slack | 5.332
Data Arrival Time | 5.038
Data Required Time | 10.370
From | svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To | svo_hdmi_inst/tmds_serdes[1]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.572 | 0.242 | tNET | RR | 1 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030 | 0.458 | tC2Q | RF | 7 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.374 | 0.343 | tNET | FF | 1 | R15C34[2][A] | svo_hdmi_inst/n147_s1/I1
2.406 | 1.032 | tINS | FF | 96 | R15C34[2][A] | svo_hdmi_inst/n147_s1/F
5.038 | 2.633 | tNET | FF | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
7.936 | 7.936 |  |  |  |  | active clock edge time
7.936 | 0.000 |  |  |  |  | u_pll/rpll_inst/CLKOUT.default_gen_clk
10.330 | 2.394 | tCL | RR | 4 | PLL_R | u_pll/rpll_inst/CLKOUT
10.445 | 0.115 | tNET | RR | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]/FCLK
10.415 | -0.030 | tUnc |  |  |  |
10.370 | -0.045 | tSu |  | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew | 1.937
Setup Relationship | 7.936
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay | cell: 1.032, 23.107%; route: 2.976, 66.630%; tC2Q: 0.458, 10.262%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.115, 100.000%

### Path6

Path Summary:

Slack | 5.332
Data Arrival Time | 5.038
Data Required Time | 10.370
From | svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To | svo_hdmi_inst/tmds_serdes[0]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.572 | 0.242 | tNET | RR | 1 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030 | 0.458 | tC2Q | RF | 7 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.374 | 0.343 | tNET | FF | 1 | R15C34[2][A] | svo_hdmi_inst/n147_s1/I1
2.406 | 1.032 | tINS | FF | 96 | R15C34[2][A] | svo_hdmi_inst/n147_s1/F
5.038 | 2.633 | tNET | FF | 1 | IOT41[A] | svo_hdmi_inst/tmds_serdes[0]/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
7.936 | 7.936 |  |  |  |  | active clock edge time
7.936 | 0.000 |  |  |  |  | u_pll/rpll_inst/CLKOUT.default_gen_clk
10.330 | 2.394 | tCL | RR | 4 | PLL_R | u_pll/rpll_inst/CLKOUT
10.445 | 0.115 | tNET | RR | 1 | IOT41[A] | svo_hdmi_inst/tmds_serdes[0]/FCLK
10.415 | -0.030 | tUnc |  |  |  |
10.370 | -0.045 | tSu |  | 1 | IOT41[A] | svo_hdmi_inst/tmds_serdes[0]

Path Statistics:

Clock Skew | 1.937
Setup Relationship | 7.936
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay | cell: 1.032, 23.107%; route: 2.976, 66.630%; tC2Q: 0.458, 10.262%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.115, 100.000%

### Path7

Path Summary:

Slack | 35.171
Data Arrival Time | 5.038
Data Required Time | 40.210
From | svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To | svo_hdmi_inst/tmds_serdes[2]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.572 | 0.242 | tNET | RR | 1 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030 | 0.458 | tC2Q | RF | 7 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.374 | 0.343 | tNET | FF | 1 | R15C34[2][A] | svo_hdmi_inst/n147_s1/I1
2.406 | 1.032 | tINS | FF | 96 | R15C34[2][A] | svo_hdmi_inst/n147_s1/F
5.038 | 2.633 | tNET | FF | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
39.682 | 39.682 |  |  |  |  | active clock edge time
39.682 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
40.255 | 0.242 | tNET | RR | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]/PCLK
40.210 | -0.045 | tSu |  | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 39.682
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay | cell: 1.032, 23.107%; route: 2.976, 66.630%; tC2Q: 0.458, 10.262%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000%

### Path8

Path Summary:

Slack | 35.171
Data Arrival Time | 5.038
Data Required Time | 40.210
From | svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To | svo_hdmi_inst/tmds_serdes[1]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.572 | 0.242 | tNET | RR | 1 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030 | 0.458 | tC2Q | RF | 7 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.374 | 0.343 | tNET | FF | 1 | R15C34[2][A] | svo_hdmi_inst/n147_s1/I1
2.406 | 1.032 | tINS | FF | 96 | R15C34[2][A] | svo_hdmi_inst/n147_s1/F
5.038 | 2.633 | tNET | FF | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
39.682 | 39.682 |  |  |  |  | active clock edge time
39.682 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
40.255 | 0.242 | tNET | RR | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]/PCLK
40.210 | -0.045 | tSu |  | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 39.682
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay | cell: 1.032, 23.107%; route: 2.976, 66.630%; tC2Q: 0.458, 10.262%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000%

### Path9

Path Summary:

Slack | 35.171
Data Arrival Time | 5.038
Data Required Time | 40.210
From | svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To | svo_hdmi_inst/tmds_serdes[0]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.572 | 0.242 | tNET | RR | 1 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030 | 0.458 | tC2Q | RF | 7 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.374 | 0.343 | tNET | FF | 1 | R15C34[2][A] | svo_hdmi_inst/n147_s1/I1
2.406 | 1.032 | tINS | FF | 96 | R15C34[2][A] | svo_hdmi_inst/n147_s1/F
5.038 | 2.633 | tNET | FF | 1 | IOT41[A] | svo_hdmi_inst/tmds_serdes[0]/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
39.682 | 39.682 |  |  |  |  | active clock edge time
39.682 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
40.255 | 0.242 | tNET | RR | 1 | IOT41[A] | svo_hdmi_inst/tmds_serdes[0]/PCLK
40.210 | -0.045 | tSu |  | 1 | IOT41[A] | svo_hdmi_inst/tmds_serdes[0]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 39.682
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay | cell: 1.032, 23.107%; route: 2.976, 66.630%; tC2Q: 0.458, 10.262%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000%

### Removal Analysis Report

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.812
Data Arrival Time | 3.333
Data Required Time | 2.521
From | svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To | svo_hdmi_inst/tmds_serdes[0]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846 | 0.333 | tC2Q | RR | 7 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.085 | 0.239 | tNET | RR | 1 | R15C34[2][A] | svo_hdmi_inst/n147_s1/I1
1.811 | 0.726 | tINS | RR | 96 | R15C34[2][A] | svo_hdmi_inst/n147_s1/F
3.333 | 1.522 | tNET | RR | 1 | IOT41[A] | svo_hdmi_inst/tmds_serdes[0]/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_pll/rpll_inst/CLKOUT.default_gen_clk
2.394 | 2.394 | tCL | RR | 4 | PLL_R | u_pll/rpll_inst/CLKOUT
2.478 | 0.085 | tNET | RR | 1 | IOT41[A] | svo_hdmi_inst/tmds_serdes[0]/FCLK
2.508 | 0.030 | tUnc |  |  |  |
2.521 | 0.012 | tHld |  | 1 | IOT41[A] | svo_hdmi_inst/tmds_serdes[0]

Path Statistics:

Clock Skew | 1.965
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay | cell: 0.726, 25.745%; route: 1.761, 62.435%; tC2Q: 0.333, 11.820%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.085, 100.000%

### Path2

Path Summary:

Slack | 0.812
Data Arrival Time | 3.333
Data Required Time | 2.521
From | svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To | svo_hdmi_inst/tmds_serdes[1]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846 | 0.333 | tC2Q | RR | 7 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.085 | 0.239 | tNET | RR | 1 | R15C34[2][A] | svo_hdmi_inst/n147_s1/I1
1.811 | 0.726 | tINS | RR | 96 | R15C34[2][A] | svo_hdmi_inst/n147_s1/F
3.333 | 1.522 | tNET | RR | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_pll/rpll_inst/CLKOUT.default_gen_clk
2.394 | 2.394 | tCL | RR | 4 | PLL_R | u_pll/rpll_inst/CLKOUT
2.478 | 0.085 | tNET | RR | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]/FCLK
2.508 | 0.030 | tUnc |  |  |  |
2.521 | 0.012 | tHld |  | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew | 1.965
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay | cell: 0.726, 25.745%; route: 1.761, 62.435%; tC2Q: 0.333, 11.820%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.085, 100.000%

### Path3

Path Summary:

Slack | 0.812
Data Arrival Time | 3.333
Data Required Time | 2.521
From | svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To | svo_hdmi_inst/tmds_serdes[2]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846 | 0.333 | tC2Q | RR | 7 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.085 | 0.239 | tNET | RR | 1 | R15C34[2][A] | svo_hdmi_inst/n147_s1/I1
1.811 | 0.726 | tINS | RR | 96 | R15C34[2][A] | svo_hdmi_inst/n147_s1/F
3.333 | 1.522 | tNET | RR | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_pll/rpll_inst/CLKOUT.default_gen_clk
2.394 | 2.394 | tCL | RR | 4 | PLL_R | u_pll/rpll_inst/CLKOUT
2.478 | 0.085 | tNET | RR | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]/FCLK
2.508 | 0.030 | tUnc |  |  |  |
2.521 | 0.012 | tHld |  | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew | 1.965
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay | cell: 0.726, 25.745%; route: 1.761, 62.435%; tC2Q: 0.333, 11.820%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.085, 100.000%

### Path4

Path Summary:

Slack | 2.807
Data Arrival Time | 3.333
Data Required Time | 0.526
From | svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To | svo_hdmi_inst/tmds_serdes[2]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846 | 0.333 | tC2Q | RR | 7 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.085 | 0.239 | tNET | RR | 1 | R15C34[2][A] | svo_hdmi_inst/n147_s1/I1
1.811 | 0.726 | tINS | RR | 96 | R15C34[2][A] | svo_hdmi_inst/n147_s1/F
3.333 | 1.522 | tNET | RR | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]/PCLK
0.526 | 0.012 | tHld |  | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay | cell: 0.726, 25.745%; route: 1.761, 62.435%; tC2Q: 0.333, 11.820%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%

### Path5

Path Summary:

Slack | 2.807
Data Arrival Time | 3.333
Data Required Time | 0.526
From | svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To | svo_hdmi_inst/tmds_serdes[1]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846 | 0.333 | tC2Q | RR | 7 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.085 | 0.239 | tNET | RR | 1 | R15C34[2][A] | svo_hdmi_inst/n147_s1/I1
1.811 | 0.726 | tINS | RR | 96 | R15C34[2][A] | svo_hdmi_inst/n147_s1/F
3.333 | 1.522 | tNET | RR | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]/PCLK
0.526 | 0.012 | tHld |  | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay | cell: 0.726, 25.745%; route: 1.761, 62.435%; tC2Q: 0.333, 11.820%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%

### Path6

Path Summary:

Slack | 2.807
Data Arrival Time | 3.333
Data Required Time | 0.526
From | svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To | svo_hdmi_inst/tmds_serdes[0]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846 | 0.333 | tC2Q | RR | 7 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.085 | 0.239 | tNET | RR | 1 | R15C34[2][A] | svo_hdmi_inst/n147_s1/I1
1.811 | 0.726 | tINS | RR | 96 | R15C34[2][A] | svo_hdmi_inst/n147_s1/F
3.333 | 1.522 | tNET | RR | 1 | IOT41[A] | svo_hdmi_inst/tmds_serdes[0]/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | IOT41[A] | svo_hdmi_inst/tmds_serdes[0]/PCLK
0.526 | 0.012 | tHld |  | 1 | IOT41[A] | svo_hdmi_inst/tmds_serdes[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay | cell: 0.726, 25.745%; route: 1.761, 62.435%; tC2Q: 0.333, 11.820%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%

### Path7

Path Summary:

Slack | 4.775
Data Arrival Time | 3.333
Data Required Time | -1.441
From | svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To | svo_hdmi_inst/tmds_serdes[2]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846 | 0.333 | tC2Q | RR | 7 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.085 | 0.239 | tNET | RR | 1 | R15C34[2][A] | svo_hdmi_inst/n147_s1/I1
1.811 | 0.726 | tINS | RR | 96 | R15C34[2][A] | svo_hdmi_inst/n147_s1/F
3.333 | 1.522 | tNET | RR | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
-3.968 | -3.968 |  |  |  |  | active clock edge time
-3.968 | 0.000 |  |  |  |  | u_pll/rpll_inst/CLKOUT.default_gen_clk
-1.574 | 2.394 | tCL | FF | 4 | PLL_R | u_pll/rpll_inst/CLKOUT
-1.484 | 0.090 | tNET | FF | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]/FCLK
-1.454 | 0.030 | tUnc |  |  |  |
-1.441 | 0.012 | tHld |  | 1 | IOT38[A] | svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew | 1.971
Hold Relationship | -3.968
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay | cell: 0.726, 25.745%; route: 1.761, 62.435%; tC2Q: 0.333, 11.820%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.090, 100.000%

### Path8

Path Summary:

Slack | 4.775
Data Arrival Time | 3.333
Data Required Time | -1.441
From | svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To | svo_hdmi_inst/tmds_serdes[1]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846 | 0.333 | tC2Q | RR | 7 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.085 | 0.239 | tNET | RR | 1 | R15C34[2][A] | svo_hdmi_inst/n147_s1/I1
1.811 | 0.726 | tINS | RR | 96 | R15C34[2][A] | svo_hdmi_inst/n147_s1/F
3.333 | 1.522 | tNET | RR | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
-3.968 | -3.968 |  |  |  |  | active clock edge time
-3.968 | 0.000 |  |  |  |  | u_pll/rpll_inst/CLKOUT.default_gen_clk
-1.574 | 2.394 | tCL | FF | 4 | PLL_R | u_pll/rpll_inst/CLKOUT
-1.484 | 0.090 | tNET | FF | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]/FCLK
-1.454 | 0.030 | tUnc |  |  |  |
-1.441 | 0.012 | tHld |  | 1 | IOT39[A] | svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew | 1.971
Hold Relationship | -3.968
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay | cell: 0.726, 25.745%; route: 1.761, 62.435%; tC2Q: 0.333, 11.820%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.090, 100.000%

### Path9

Path Summary:

Slack | 4.775
Data Arrival Time | 3.333
Data Required Time | -1.441
From | svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To | svo_hdmi_inst/tmds_serdes[0]
Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330 | 0.330 | tCL | RR | 549 | TOPSIDE[0] | u_div_5/clkdiv_inst/CLKOUT
0.513 | 0.183 | tNET | RR | 1 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846 | 0.333 | tC2Q | RR | 7 | R15C34[0][A] | svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.085 | 0.239 | tNET | RR | 1 | R15C34[2][A] | svo_hdmi_inst/n147_s1/I1
1.811 | 0.726 | tINS | RR | 96 | R15C34[2][A] | svo_hdmi_inst/n147_s1/F
3.333 | 1.522 | tNET | RR | 1 | IOT41[A] | svo_hdmi_inst/tmds_serdes[0]/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
-3.968 | -3.968 |  |  |  |  | active clock edge time
-3.968 | 0.000 |  |  |  |  | u_pll/rpll_inst/CLKOUT.default_gen_clk
-1.574 | 2.394 | tCL | FF | 4 | PLL_R | u_pll/rpll_inst/CLKOUT
-1.484 | 0.090 | tNET | FF | 1 | IOT41[A] | svo_hdmi_inst/tmds_serdes[0]/FCLK
-1.454 | 0.030 | tUnc |  |  |  |
-1.441 | 0.012 | tHld |  | 1 | IOT41[A] | svo_hdmi_inst/tmds_serdes[0]

Path Statistics:

Clock Skew | 1.971
Hold Relationship | -3.968
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay | cell: 0.726, 25.745%; route: 1.761, 62.435%; tC2Q: 0.333, 11.820%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.090, 100.000%

## Minimum Pulse Width Report:

#### Report Command:report_min_pulse_width -nworst 10 -detail

### MPW1

MPW Summary:

Slack: | 7.300
Actual Width: | 8.550
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | cpuclk
Objects: | spi_1/divider_12_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | cpuclk
10.000 | 0.000 | tCL | FF | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | spi_1/divider_12_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | cpuclk
20.000 | 0.000 | tCL | RR | cpuclk_ibuf/I
21.392 | 1.392 | tINS | RR | cpuclk_ibuf/O
22.410 | 1.018 | tNET | RR | spi_1/divider_12_s0/CLK

### MPW2

MPW Summary:

Slack: | 7.300
Actual Width: | 8.550
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | cpuclk
Objects: | spi_1/divider_10_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | cpuclk
10.000 | 0.000 | tCL | FF | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | spi_1/divider_10_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | cpuclk
20.000 | 0.000 | tCL | RR | cpuclk_ibuf/I
21.392 | 1.392 | tINS | RR | cpuclk_ibuf/O
22.410 | 1.018 | tNET | RR | spi_1/divider_10_s0/CLK

### MPW3

MPW Summary:

Slack: | 7.300
Actual Width: | 8.550
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | cpuclk
Objects: | spi_1/divider_6_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | cpuclk
10.000 | 0.000 | tCL | FF | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | spi_1/divider_6_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | cpuclk
20.000 | 0.000 | tCL | RR | cpuclk_ibuf/I
21.392 | 1.392 | tINS | RR | cpuclk_ibuf/O
22.410 | 1.018 | tNET | RR | spi_1/divider_6_s0/CLK

### MPW4

MPW Summary:

Slack: | 7.300
Actual Width: | 8.550
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | cpuclk
Objects: | spi_1/data_tx_7_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | cpuclk
10.000 | 0.000 | tCL | FF | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | spi_1/data_tx_7_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | cpuclk
20.000 | 0.000 | tCL | RR | cpuclk_ibuf/I
21.392 | 1.392 | tINS | RR | cpuclk_ibuf/O
22.410 | 1.018 | tNET | RR | spi_1/data_tx_7_s0/CLK

### MPW5

MPW Summary:

Slack: | 7.300
Actual Width: | 8.550
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | cpuclk
Objects: | spi_1/data_rx_3_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | cpuclk
10.000 | 0.000 | tCL | FF | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | spi_1/data_rx_3_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | cpuclk
20.000 | 0.000 | tCL | RR | cpuclk_ibuf/I
21.392 | 1.392 | tINS | RR | cpuclk_ibuf/O
22.410 | 1.018 | tNET | RR | spi_1/data_rx_3_s0/CLK

### MPW6

MPW Summary:

Slack: | 7.300
Actual Width: | 8.550
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | cpuclk
Objects: | serial_1/txdata_2_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | cpuclk
10.000 | 0.000 | tCL | FF | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | serial_1/txdata_2_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | cpuclk
20.000 | 0.000 | tCL | RR | cpuclk_ibuf/I
21.392 | 1.392 | tINS | RR | cpuclk_ibuf/O
22.410 | 1.018 | tNET | RR | serial_1/txdata_2_s0/CLK

### MPW7

MPW Summary:

Slack: | 7.300
Actual Width: | 8.550
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | cpuclk
Objects: | test1/r0_5_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | cpuclk
10.000 | 0.000 | tCL | FF | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | test1/r0_5_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | cpuclk
20.000 | 0.000 | tCL | RR | cpuclk_ibuf/I
21.392 | 1.392 | tINS | RR | cpuclk_ibuf/O
22.410 | 1.018 | tNET | RR | test1/r0_5_s0/CLK

### MPW8

MPW Summary:

Slack: | 7.300
Actual Width: | 8.550
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | cpuclk
Objects: | test1/toneB/divider_11_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | cpuclk
10.000 | 0.000 | tCL | FF | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | test1/toneB/divider_11_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | cpuclk
20.000 | 0.000 | tCL | RR | cpuclk_ibuf/I
21.392 | 1.392 | tINS | RR | cpuclk_ibuf/O
22.410 | 1.018 | tNET | RR | test1/toneB/divider_11_s0/CLK

### MPW9

MPW Summary:

Slack: | 7.300
Actual Width: | 8.550
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | cpuclk
Objects: | svo_hdmi_inst/svo_tcard/bramwraddr_11_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | cpuclk
10.000 | 0.000 | tCL | FF | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | svo_hdmi_inst/svo_tcard/bramwraddr_11_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | cpuclk
20.000 | 0.000 | tCL | RR | cpuclk_ibuf/I
21.392 | 1.392 | tINS | RR | cpuclk_ibuf/O
22.410 | 1.018 | tNET | RR | svo_hdmi_inst/svo_tcard/bramwraddr_11_s0/CLK

### MPW10

MPW Summary:

Slack: | 7.300
Actual Width: | 8.550
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | cpuclk
Objects: | svo_hdmi_inst/svo_tcard/bramwraddr_12_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | cpuclk
10.000 | 0.000 | tCL | FF | cpuclk_ibuf/I
12.314 | 2.314 | tINS | FF | cpuclk_ibuf/O
13.860 | 1.546 | tNET | FF | svo_hdmi_inst/svo_tcard/bramwraddr_12_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | cpuclk
20.000 | 0.000 | tCL | RR | cpuclk_ibuf/I
21.392 | 1.392 | tINS | RR | cpuclk_ibuf/O
22.410 | 1.018 | tNET | RR | svo_hdmi_inst/svo_tcard/bramwraddr_12_s0/CLK

## High Fanout Nets Report:

#### Report Command:report_high_fanout_nets -max_nets 10

FANOUT | NET NAME | WORST SLACK | MAX DELAY
--- | --- | --- | ---
563 | cpuclk_d | -14.411 | 1.546
549 | clk_p | 1.370 | 0.659
96 | svo_hdmi_inst/n147_5 | 1.370 | 3.117
57 | svo_hdmi_inst/n1716_6 | 15.384 | 3.630
56 | svo_hdmi_inst/svo_enc/pixel_fifo_rdaddr[2] | 27.045 | 3.448
40 | svo_hdmi_inst/svo_tcard/your_instance_name/dff_q_7 | 10.722 | 1.903
39 | svo_hdmi_inst/svo_overlay/svo_buf_in/n169_7 | 33.051 | 1.820
39 | svo_hdmi_inst/svo_overlay/svo_buf_out/n169_5 | 31.096 | 1.808
34 | svo_hdmi_inst/svo_term/oresetn | 34.625 | 1.964
32 | svo_hdmi_inst/svo_tcard/n2542_6 | 15.297 | 2.276

## Route Congestions Report:

#### Report Command:report_route_congestion -max_grids 10

GRID LOC | ROUTE CONGESTIONS
--- | ---
R2C2 | 100.00%
R2C9 | 100.00%
R2C13 | 100.00%
R2C15 | 100.00%
R2C16 | 100.00%
R3C3 | 100.00%
R4C22 | 100.00%
R12C42 | 100.00%
R12C43 | 100.00%
R24C17 | 100.00%

## Timing Exceptions Report:

### Setup Analysis Report

#### Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Hold Analysis Report

#### Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Recovery Analysis Report

#### Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Removal Analysis Report

#### Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

## Timing Constraints Report:

SDC Command Type | State | Detail Command
--- | --- | ---
TC_CLOCK | Actived | create_clock -name clk_osc -period 37.037 -waveform {0 18.518} [get_ports {clk}]