Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | Z:\hdmi\src\PS2_module.v Z:\hdmi\src\SERIAL_module.v Z:\hdmi\src\SOUND_module.v Z:\hdmi\src\SPI_module.v Z:\hdmi\src\TIMER_module.v Z:\hdmi\src\gowin_clkdiv\gowin_clkdiv.v Z:\hdmi\src\gowin_dpb\gowin_dpb.v Z:\hdmi\src\gowin_rpll\gowin_rpll.v Z:\hdmi\src\hdmi\svo_defines.vh Z:\hdmi\src\hdmi\svo_enc.v Z:\hdmi\src\hdmi\svo_openldi.v Z:\hdmi\src\hdmi\svo_tcard.v Z:\hdmi\src\hdmi\svo_term.v Z:\hdmi\src\hdmi\svo_tmds.v Z:\hdmi\src\hdmi\svo_utils.v Z:\hdmi\src\hdmi\svo_vdma.v Z:\hdmi\src\svo_hdmi.v Z:\hdmi\src\termfont_new.vh Z:\hdmi\src\termfont_old.vh Z:\hdmi\src\top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12 (64-bit) |
| Part Number | GW1NR-LV9QN88PC6/I5 |
| Device | GW1NR-9 |
| Device Version | C |
| Created Time | Wed Apr 1 21:06:37 2026 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 212.996MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.232s, Peak memory usage = 212.996MB Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.056s, Peak memory usage = 212.996MB Optimizing Phase 2: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.231s, Peak memory usage = 212.996MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.08s, Peak memory usage = 212.996MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 212.996MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 212.996MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 212.996MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.217s, Peak memory usage = 212.996MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 212.996MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 212.996MB Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 222.461MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.256s, Peak memory usage = 222.461MB Generate output files: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.152s, Peak memory usage = 222.461MB |
| Total Time and Memory Usage | CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 222.461MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 47 |
| I/O Buf | 43 |
| IBUF | 13 |
| OBUF | 16 |
| IOBUF | 10 |
| ELVDS_OBUF | 4 |
| Register | 1104 |
| DFF | 88 |
| DFFE | 371 |
| DFFS | 2 |
| DFFSE | 25 |
| DFFR | 156 |
| DFFRE | 458 |
| DFFC | 4 |
| LUT | 1520 |
| LUT2 | 184 |
| LUT3 | 464 |
| LUT4 | 870 |
| LUT5 | 2 |
| MUX | 144 |
| MUX2 | 144 |
| ALU | 361 |
| ALU | 361 |
| SSRAM | 4 |
| RAM16SDP4 | 4 |
| INV | 28 |
| INV | 28 |
| IOLOGIC | 3 |
| OSER10 | 3 |
| BSRAM | 20 |
| DPB | 19 |
| pROM | 1 |
| CLOCK | 2 |
| CLKDIV | 1 |
| rPLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 2079(1694 LUT, 361 ALU, 4 RAM16) / 8640 | 25% |
| Register | 1104 / 6693 | 17% |
| --Register as Latch | 0 / 6693 | 0% |
| --Register as FF | 1104 / 6693 | 17% |
| BSRAM | 20 / 26 | 77% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 37.037 | 27.000 | 0.000 | 18.519 | clk_ibuf/I | ||
| 2 | cpuclk | Base | 20.000 | 50.000 | 0.000 | 10.000 | cpuclk_ibuf/I | ||
| 3 | svo_hdmi_inst/svo_tcard/bram_aclock | Base | 20.000 | 50.000 | 0.000 | 10.000 | svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q | ||
| 4 | test1/wng1/fsr_clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | test1/wng1/fsr_clk_s0/Q | ||
| 5 | u_pll/rpll_inst/CLKOUT.default_gen_clk | Generated | 7.937 | 126.000 | 0.000 | 3.968 | clk_ibuf/I | clk | u_pll/rpll_inst/CLKOUT |
| 6 | u_pll/rpll_inst/CLKOUTP.default_gen_clk | Generated | 7.937 | 126.000 | 0.000 | 3.968 | clk_ibuf/I | clk | u_pll/rpll_inst/CLKOUTP |
| 7 | u_pll/rpll_inst/CLKOUTD.default_gen_clk | Generated | 15.873 | 63.000 | 0.000 | 7.937 | clk_ibuf/I | clk | u_pll/rpll_inst/CLKOUTD |
| 8 | u_pll/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 23.810 | 42.000 | 0.000 | 11.905 | clk_ibuf/I | clk | u_pll/rpll_inst/CLKOUTD3 |
| 9 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | Generated | 39.683 | 25.200 | 0.000 | 19.841 | u_pll/rpll_inst/CLKOUT | u_pll/rpll_inst/CLKOUT.default_gen_clk | u_div_5/clkdiv_inst/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | cpuclk | 50.000(MHz) | 24.420(MHz) | 24 | TOP |
| 2 | test1/wng1/fsr_clk | 50.000(MHz) | 257.909(MHz) | 2 | TOP |
| 3 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | 25.200(MHz) | 30.249(MHz) | 10 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -20.950 |
| Data Arrival Time | 41.276 |
| Data Required Time | 20.326 |
| From | test1/wng1/noiseact_s0 |
| To | test1/dac1/outshr_10_s0 |
| Launch Clk | cpuclk[R] |
| Latch Clk | cpuclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | cpuclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 563 | cpuclk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | test1/wng1/noiseact_s0/CLK |
| 1.184 | 0.458 | tC2Q | RF | 27 | test1/wng1/noiseact_s0/Q |
| 2.144 | 0.960 | tNET | FF | 1 | test1/w001_11_s3/I1 |
| 3.243 | 1.099 | tINS | FF | 6 | test1/w001_11_s3/F |
| 4.203 | 0.960 | tNET | FF | 1 | test1/w001_6_s6/I3 |
| 4.829 | 0.626 | tINS | FF | 3 | test1/w001_6_s6/F |
| 5.789 | 0.960 | tNET | FF | 1 | test1/w001_6_s7/I0 |
| 6.821 | 1.032 | tINS | FF | 2 | test1/w001_6_s7/F |
| 7.781 | 0.960 | tNET | FF | 2 | test1/n376_s/I0 |
| 8.764 | 0.983 | tINS | FF | 1 | test1/n376_s/SUM |
| 9.724 | 0.960 | tNET | FF | 1 | test1/w002_6_s3/I0 |
| 10.756 | 1.032 | tINS | FF | 2 | test1/w002_6_s3/F |
| 11.716 | 0.960 | tNET | FF | 1 | test1/w002_6_s0/I1 |
| 12.815 | 1.099 | tINS | FF | 2 | test1/w002_6_s0/F |
| 13.775 | 0.960 | tNET | FF | 2 | test1/n552_s/I0 |
| 14.758 | 0.983 | tINS | FF | 2 | test1/n552_s/SUM |
| 15.718 | 0.960 | tNET | FF | 1 | test1/w003_6_s7/I0 |
| 16.750 | 1.032 | tINS | FF | 2 | test1/w003_6_s7/F |
| 17.710 | 0.960 | tNET | FF | 1 | test1/w003_6_s3/I3 |
| 18.336 | 0.626 | tINS | FF | 2 | test1/w003_6_s3/F |
| 19.296 | 0.960 | tNET | FF | 1 | test1/w003_6_s1/I3 |
| 19.922 | 0.626 | tINS | FF | 2 | test1/w003_6_s1/F |
| 20.882 | 0.960 | tNET | FF | 1 | test1/w003_6_s0/I2 |
| 21.704 | 0.822 | tINS | FF | 1 | test1/w003_6_s0/F |
| 22.664 | 0.960 | tNET | FF | 2 | test1/n670_1_s/I0 |
| 23.622 | 0.958 | tINS | FF | 1 | test1/n670_1_s/COUT |
| 23.622 | 0.000 | tNET | FF | 2 | test1/n669_1_s/CIN |
| 23.679 | 0.057 | tINS | FF | 1 | test1/n669_1_s/COUT |
| 23.679 | 0.000 | tNET | FF | 2 | test1/n668_1_s/CIN |
| 24.242 | 0.563 | tINS | FF | 1 | test1/n668_1_s/SUM |
| 25.202 | 0.960 | tNET | FF | 1 | test1/w004_8_s2/I2 |
| 26.024 | 0.822 | tINS | FF | 3 | test1/w004_8_s2/F |
| 26.984 | 0.960 | tNET | FF | 1 | test1/w004_8_s0/I2 |
| 27.806 | 0.822 | tINS | FF | 1 | test1/w004_8_s0/F |
| 28.766 | 0.960 | tNET | FF | 2 | test1/n702_1_s/I0 |
| 29.724 | 0.958 | tINS | FF | 1 | test1/n702_1_s/COUT |
| 29.724 | 0.000 | tNET | FF | 2 | test1/n701_1_s/CIN |
| 30.287 | 0.563 | tINS | FF | 1 | test1/n701_1_s/SUM |
| 31.247 | 0.960 | tNET | FF | 1 | test1/w005_9_s7/I0 |
| 32.279 | 1.032 | tINS | FF | 2 | test1/w005_9_s7/F |
| 33.239 | 0.960 | tNET | FF | 1 | test1/w005_9_s0/I2 |
| 34.061 | 0.822 | tINS | FF | 1 | test1/w005_9_s0/F |
| 35.021 | 0.960 | tNET | FF | 2 | test1/n735_1_s/I0 |
| 35.979 | 0.958 | tINS | FF | 1 | test1/n735_1_s/COUT |
| 35.979 | 0.000 | tNET | FF | 2 | test1/n734_1_s/CIN |
| 36.542 | 0.563 | tINS | FF | 1 | test1/n734_1_s/SUM |
| 37.502 | 0.960 | tNET | FF | 1 | test1/dac1/n19_s1/I2 |
| 38.324 | 0.822 | tINS | FF | 1 | test1/dac1/n19_s1/F |
| 39.284 | 0.960 | tNET | FF | 1 | test1/dac1/n19_s0/I0 |
| 40.316 | 1.032 | tINS | FF | 1 | test1/dac1/n19_s0/F |
| 41.276 | 0.960 | tNET | FF | 1 | test1/dac1/outshr_10_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | cpuclk | |||
| 20.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 563 | cpuclk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | test1/dac1/outshr_10_s0/CLK |
| 20.326 | -0.400 | tSu | 1 | test1/dac1/outshr_10_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 24 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 19.932, 49.154%; route: 20.160, 49.716%; tC2Q: 0.458, 1.130% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 2
Path Summary:| Slack | -20.772 |
| Data Arrival Time | 41.098 |
| Data Required Time | 20.326 |
| From | test1/env1/env_amp_1_s0 |
| To | test1/dac1/outshr_11_s0 |
| Launch Clk | cpuclk[R] |
| Latch Clk | cpuclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | cpuclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 563 | cpuclk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | test1/env1/env_amp_1_s0/CLK |
| 1.184 | 0.458 | tC2Q | RF | 12 | test1/env1/env_amp_1_s0/Q |
| 2.144 | 0.960 | tNET | FF | 1 | test1/ampA_1_s0/I1 |
| 3.243 | 1.099 | tINS | FF | 5 | test1/ampA_1_s0/F |
| 4.203 | 0.960 | tNET | FF | 1 | test1/w001_8_s2/I1 |
| 5.302 | 1.099 | tINS | FF | 1 | test1/w001_8_s2/F |
| 6.262 | 0.960 | tNET | FF | 1 | test1/w001_8_s1/I0 |
| 7.294 | 1.032 | tINS | FF | 3 | test1/w001_8_s1/F |
| 8.254 | 0.960 | tNET | FF | 1 | test1/w001_8_s0/I2 |
| 9.076 | 0.822 | tINS | FF | 2 | test1/w001_8_s0/F |
| 10.036 | 0.960 | tNET | FF | 2 | test1/n374_s/I0 |
| 10.994 | 0.958 | tINS | FF | 1 | test1/n374_s/COUT |
| 10.994 | 0.000 | tNET | FF | 2 | test1/n373_s/CIN |
| 11.051 | 0.057 | tINS | FF | 1 | test1/n373_s/COUT |
| 11.051 | 0.000 | tNET | FF | 2 | test1/n372_s/CIN |
| 11.614 | 0.563 | tINS | FF | 2 | test1/n372_s/SUM |
| 12.574 | 0.960 | tNET | FF | 1 | test1/w002_11_s7/I1 |
| 13.673 | 1.099 | tINS | FF | 1 | test1/w002_11_s7/F |
| 14.633 | 0.960 | tNET | FF | 1 | test1/w002_11_s6/I0 |
| 15.665 | 1.032 | tINS | FF | 1 | test1/w002_11_s6/F |
| 16.625 | 0.960 | tNET | FF | 1 | test1/w002_11_s2/I0 |
| 17.657 | 1.032 | tINS | FF | 2 | test1/w002_11_s2/F |
| 18.617 | 0.960 | tNET | FF | 1 | test1/w002_11_s0/I1 |
| 19.716 | 1.099 | tINS | FF | 2 | test1/w002_11_s0/F |
| 20.676 | 0.960 | tNET | FF | 2 | test1/n547_s/I0 |
| 21.659 | 0.983 | tINS | FF | 1 | test1/n547_s/SUM |
| 22.619 | 0.960 | tNET | FF | 1 | test1/w003_11_s3/I1 |
| 23.718 | 1.099 | tINS | FF | 2 | test1/w003_11_s3/F |
| 24.678 | 0.960 | tNET | FF | 1 | test1/w003_11_s2/I3 |
| 25.304 | 0.626 | tINS | FF | 3 | test1/w003_11_s2/F |
| 26.264 | 0.960 | tNET | FF | 1 | test1/w003_11_s5/I3 |
| 26.890 | 0.626 | tINS | FF | 1 | test1/w003_11_s5/F |
| 27.850 | 0.960 | tNET | FF | 2 | test1/n665_1_s/I0 |
| 28.833 | 0.983 | tINS | FF | 2 | test1/n665_1_s/SUM |
| 29.793 | 0.960 | tNET | FF | 1 | test1/w004_11_s0/I2 |
| 30.615 | 0.822 | tINS | FF | 1 | test1/w004_11_s0/F |
| 31.575 | 0.960 | tNET | FF | 2 | test1/n699_1_s/I0 |
| 32.558 | 0.983 | tINS | FF | 1 | test1/n699_1_s/SUM |
| 33.518 | 0.960 | tNET | FF | 1 | test1/w005_11_s3/I0 |
| 34.550 | 1.032 | tINS | FF | 2 | test1/w005_11_s3/F |
| 35.510 | 0.960 | tNET | FF | 1 | test1/w005_11_s0/I3 |
| 36.136 | 0.626 | tINS | FF | 1 | test1/w005_11_s0/F |
| 37.096 | 0.960 | tNET | FF | 2 | test1/n733_1_s/I0 |
| 38.079 | 0.983 | tINS | FF | 1 | test1/n733_1_s/SUM |
| 39.039 | 0.960 | tNET | FF | 1 | test1/dac1/n18_s1/I1 |
| 40.138 | 1.099 | tINS | FF | 1 | test1/dac1/n18_s1/F |
| 41.098 | 0.960 | tNET | FF | 1 | test1/dac1/outshr_11_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | cpuclk | |||
| 20.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 563 | cpuclk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | test1/dac1/outshr_11_s0/CLK |
| 20.326 | -0.400 | tSu | 1 | test1/dac1/outshr_11_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 22 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 19.754, 48.930%; route: 20.160, 49.935%; tC2Q: 0.458, 1.135% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 3
Path Summary:| Slack | -20.479 |
| Data Arrival Time | 40.805 |
| Data Required Time | 20.326 |
| From | test1/wng1/noiseact_s0 |
| To | test1/dac1/outshr_9_s0 |
| Launch Clk | cpuclk[R] |
| Latch Clk | cpuclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | cpuclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 563 | cpuclk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | test1/wng1/noiseact_s0/CLK |
| 1.184 | 0.458 | tC2Q | RF | 27 | test1/wng1/noiseact_s0/Q |
| 2.144 | 0.960 | tNET | FF | 1 | test1/w001_11_s3/I1 |
| 3.243 | 1.099 | tINS | FF | 6 | test1/w001_11_s3/F |
| 4.203 | 0.960 | tNET | FF | 1 | test1/w001_6_s6/I3 |
| 4.829 | 0.626 | tINS | FF | 3 | test1/w001_6_s6/F |
| 5.789 | 0.960 | tNET | FF | 1 | test1/w001_6_s7/I0 |
| 6.821 | 1.032 | tINS | FF | 2 | test1/w001_6_s7/F |
| 7.781 | 0.960 | tNET | FF | 2 | test1/n376_s/I0 |
| 8.764 | 0.983 | tINS | FF | 1 | test1/n376_s/SUM |
| 9.724 | 0.960 | tNET | FF | 1 | test1/w002_6_s3/I0 |
| 10.756 | 1.032 | tINS | FF | 2 | test1/w002_6_s3/F |
| 11.716 | 0.960 | tNET | FF | 1 | test1/w002_6_s0/I1 |
| 12.815 | 1.099 | tINS | FF | 2 | test1/w002_6_s0/F |
| 13.775 | 0.960 | tNET | FF | 2 | test1/n552_s/I0 |
| 14.758 | 0.983 | tINS | FF | 2 | test1/n552_s/SUM |
| 15.718 | 0.960 | tNET | FF | 1 | test1/w003_6_s7/I0 |
| 16.750 | 1.032 | tINS | FF | 2 | test1/w003_6_s7/F |
| 17.710 | 0.960 | tNET | FF | 1 | test1/w003_6_s3/I3 |
| 18.336 | 0.626 | tINS | FF | 2 | test1/w003_6_s3/F |
| 19.296 | 0.960 | tNET | FF | 1 | test1/w003_6_s1/I3 |
| 19.922 | 0.626 | tINS | FF | 2 | test1/w003_6_s1/F |
| 20.882 | 0.960 | tNET | FF | 1 | test1/w003_6_s0/I2 |
| 21.704 | 0.822 | tINS | FF | 1 | test1/w003_6_s0/F |
| 22.664 | 0.960 | tNET | FF | 2 | test1/n670_1_s/I0 |
| 23.622 | 0.958 | tINS | FF | 1 | test1/n670_1_s/COUT |
| 23.622 | 0.000 | tNET | FF | 2 | test1/n669_1_s/CIN |
| 23.679 | 0.057 | tINS | FF | 1 | test1/n669_1_s/COUT |
| 23.679 | 0.000 | tNET | FF | 2 | test1/n668_1_s/CIN |
| 24.242 | 0.563 | tINS | FF | 1 | test1/n668_1_s/SUM |
| 25.202 | 0.960 | tNET | FF | 1 | test1/w004_8_s2/I2 |
| 26.024 | 0.822 | tINS | FF | 3 | test1/w004_8_s2/F |
| 26.984 | 0.960 | tNET | FF | 1 | test1/w004_8_s0/I2 |
| 27.806 | 0.822 | tINS | FF | 1 | test1/w004_8_s0/F |
| 28.766 | 0.960 | tNET | FF | 2 | test1/n702_1_s/I0 |
| 29.724 | 0.958 | tINS | FF | 1 | test1/n702_1_s/COUT |
| 29.724 | 0.000 | tNET | FF | 2 | test1/n701_1_s/CIN |
| 30.287 | 0.563 | tINS | FF | 1 | test1/n701_1_s/SUM |
| 31.247 | 0.960 | tNET | FF | 1 | test1/w005_9_s7/I0 |
| 32.279 | 1.032 | tINS | FF | 2 | test1/w005_9_s7/F |
| 33.239 | 0.960 | tNET | FF | 1 | test1/w005_9_s0/I2 |
| 34.061 | 0.822 | tINS | FF | 1 | test1/w005_9_s0/F |
| 35.021 | 0.960 | tNET | FF | 2 | test1/n735_1_s/I0 |
| 36.004 | 0.983 | tINS | FF | 1 | test1/n735_1_s/SUM |
| 36.964 | 0.960 | tNET | FF | 1 | test1/dac1/n20_s1/I2 |
| 37.786 | 0.822 | tINS | FF | 1 | test1/dac1/n20_s1/F |
| 38.746 | 0.960 | tNET | FF | 1 | test1/dac1/n20_s0/I1 |
| 39.845 | 1.099 | tINS | FF | 1 | test1/dac1/n20_s0/F |
| 40.805 | 0.960 | tNET | FF | 1 | test1/dac1/outshr_9_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | cpuclk | |||
| 20.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 563 | cpuclk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | test1/dac1/outshr_9_s0/CLK |
| 20.326 | -0.400 | tSu | 1 | test1/dac1/outshr_9_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 23 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 19.461, 48.556%; route: 20.160, 50.300%; tC2Q: 0.458, 1.144% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 4
Path Summary:| Slack | -18.864 |
| Data Arrival Time | 39.190 |
| Data Required Time | 20.326 |
| From | test1/wng1/noiseact_s0 |
| To | test1/dac1/outshr_8_s0 |
| Launch Clk | cpuclk[R] |
| Latch Clk | cpuclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | cpuclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 563 | cpuclk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | test1/wng1/noiseact_s0/CLK |
| 1.184 | 0.458 | tC2Q | RF | 27 | test1/wng1/noiseact_s0/Q |
| 2.144 | 0.960 | tNET | FF | 1 | test1/w001_11_s3/I1 |
| 3.243 | 1.099 | tINS | FF | 6 | test1/w001_11_s3/F |
| 4.203 | 0.960 | tNET | FF | 1 | test1/w001_6_s6/I3 |
| 4.829 | 0.626 | tINS | FF | 3 | test1/w001_6_s6/F |
| 5.789 | 0.960 | tNET | FF | 1 | test1/w001_6_s7/I0 |
| 6.821 | 1.032 | tINS | FF | 2 | test1/w001_6_s7/F |
| 7.781 | 0.960 | tNET | FF | 2 | test1/n376_s/I0 |
| 8.764 | 0.983 | tINS | FF | 1 | test1/n376_s/SUM |
| 9.724 | 0.960 | tNET | FF | 1 | test1/w002_6_s3/I0 |
| 10.756 | 1.032 | tINS | FF | 2 | test1/w002_6_s3/F |
| 11.716 | 0.960 | tNET | FF | 1 | test1/w002_6_s0/I1 |
| 12.815 | 1.099 | tINS | FF | 2 | test1/w002_6_s0/F |
| 13.775 | 0.960 | tNET | FF | 2 | test1/n552_s/I0 |
| 14.758 | 0.983 | tINS | FF | 2 | test1/n552_s/SUM |
| 15.718 | 0.960 | tNET | FF | 1 | test1/w003_6_s7/I0 |
| 16.750 | 1.032 | tINS | FF | 2 | test1/w003_6_s7/F |
| 17.710 | 0.960 | tNET | FF | 1 | test1/w003_6_s3/I3 |
| 18.336 | 0.626 | tINS | FF | 2 | test1/w003_6_s3/F |
| 19.296 | 0.960 | tNET | FF | 1 | test1/w003_6_s1/I3 |
| 19.922 | 0.626 | tINS | FF | 2 | test1/w003_6_s1/F |
| 20.882 | 0.960 | tNET | FF | 1 | test1/w003_6_s0/I2 |
| 21.704 | 0.822 | tINS | FF | 1 | test1/w003_6_s0/F |
| 22.664 | 0.960 | tNET | FF | 2 | test1/n670_1_s/I0 |
| 23.647 | 0.983 | tINS | FF | 1 | test1/n670_1_s/SUM |
| 24.607 | 0.960 | tNET | FF | 1 | test1/w004_6_s3/I0 |
| 25.639 | 1.032 | tINS | FF | 3 | test1/w004_6_s3/F |
| 26.599 | 0.960 | tNET | FF | 1 | test1/w004_6_s0/I3 |
| 27.225 | 0.626 | tINS | FF | 1 | test1/w004_6_s0/F |
| 28.185 | 0.960 | tNET | FF | 2 | test1/n704_1_s/I0 |
| 29.143 | 0.958 | tINS | FF | 1 | test1/n704_1_s/COUT |
| 29.143 | 0.000 | tNET | FF | 2 | test1/n703_1_s/CIN |
| 29.706 | 0.563 | tINS | FF | 1 | test1/n703_1_s/SUM |
| 30.666 | 0.960 | tNET | FF | 1 | test1/w005_7_s4/I1 |
| 31.765 | 1.099 | tINS | FF | 2 | test1/w005_7_s4/F |
| 32.725 | 0.960 | tNET | FF | 2 | test1/n737_1_s/I0 |
| 33.683 | 0.958 | tINS | FF | 1 | test1/n737_1_s/COUT |
| 33.683 | 0.000 | tNET | FF | 2 | test1/n736_1_s/CIN |
| 34.246 | 0.563 | tINS | FF | 1 | test1/n736_1_s/SUM |
| 35.206 | 0.960 | tNET | FF | 1 | test1/dac1/n21_s3/I0 |
| 36.238 | 1.032 | tINS | FF | 1 | test1/dac1/n21_s3/F |
| 37.198 | 0.960 | tNET | FF | 1 | test1/dac1/n21_s0/I0 |
| 38.230 | 1.032 | tINS | FF | 1 | test1/dac1/n21_s0/F |
| 39.190 | 0.960 | tNET | FF | 1 | test1/dac1/outshr_8_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | cpuclk | |||
| 20.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 563 | cpuclk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | test1/dac1/outshr_8_s0/CLK |
| 20.326 | -0.400 | tSu | 1 | test1/dac1/outshr_8_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 22 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 18.806, 48.892%; route: 19.200, 49.916%; tC2Q: 0.458, 1.192% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 5
Path Summary:| Slack | -18.460 |
| Data Arrival Time | 38.786 |
| Data Required Time | 20.326 |
| From | test1/wng1/noiseact_s0 |
| To | test1/dac1/outshr_7_s0 |
| Launch Clk | cpuclk[R] |
| Latch Clk | cpuclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | cpuclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 563 | cpuclk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | test1/wng1/noiseact_s0/CLK |
| 1.184 | 0.458 | tC2Q | RF | 27 | test1/wng1/noiseact_s0/Q |
| 2.144 | 0.960 | tNET | FF | 1 | test1/w001_11_s3/I1 |
| 3.243 | 1.099 | tINS | FF | 6 | test1/w001_11_s3/F |
| 4.203 | 0.960 | tNET | FF | 1 | test1/w001_6_s6/I3 |
| 4.829 | 0.626 | tINS | FF | 3 | test1/w001_6_s6/F |
| 5.789 | 0.960 | tNET | FF | 1 | test1/w001_6_s7/I0 |
| 6.821 | 1.032 | tINS | FF | 2 | test1/w001_6_s7/F |
| 7.781 | 0.960 | tNET | FF | 2 | test1/n376_s/I0 |
| 8.764 | 0.983 | tINS | FF | 1 | test1/n376_s/SUM |
| 9.724 | 0.960 | tNET | FF | 1 | test1/w002_6_s3/I0 |
| 10.756 | 1.032 | tINS | FF | 2 | test1/w002_6_s3/F |
| 11.716 | 0.960 | tNET | FF | 1 | test1/w002_6_s0/I1 |
| 12.815 | 1.099 | tINS | FF | 2 | test1/w002_6_s0/F |
| 13.775 | 0.960 | tNET | FF | 2 | test1/n552_s/I0 |
| 14.758 | 0.983 | tINS | FF | 2 | test1/n552_s/SUM |
| 15.718 | 0.960 | tNET | FF | 1 | test1/w003_6_s7/I0 |
| 16.750 | 1.032 | tINS | FF | 2 | test1/w003_6_s7/F |
| 17.710 | 0.960 | tNET | FF | 1 | test1/w003_6_s3/I3 |
| 18.336 | 0.626 | tINS | FF | 2 | test1/w003_6_s3/F |
| 19.296 | 0.960 | tNET | FF | 1 | test1/w003_6_s1/I3 |
| 19.922 | 0.626 | tINS | FF | 2 | test1/w003_6_s1/F |
| 20.882 | 0.960 | tNET | FF | 1 | test1/w003_6_s0/I2 |
| 21.704 | 0.822 | tINS | FF | 1 | test1/w003_6_s0/F |
| 22.664 | 0.960 | tNET | FF | 2 | test1/n670_1_s/I0 |
| 23.647 | 0.983 | tINS | FF | 1 | test1/n670_1_s/SUM |
| 24.607 | 0.960 | tNET | FF | 1 | test1/w004_6_s3/I0 |
| 25.639 | 1.032 | tINS | FF | 3 | test1/w004_6_s3/F |
| 26.599 | 0.960 | tNET | FF | 1 | test1/w004_6_s0/I3 |
| 27.225 | 0.626 | tINS | FF | 1 | test1/w004_6_s0/F |
| 28.185 | 0.960 | tNET | FF | 2 | test1/n704_1_s/I0 |
| 29.143 | 0.958 | tINS | FF | 1 | test1/n704_1_s/COUT |
| 29.143 | 0.000 | tNET | FF | 2 | test1/n703_1_s/CIN |
| 29.706 | 0.563 | tINS | FF | 1 | test1/n703_1_s/SUM |
| 30.666 | 0.960 | tNET | FF | 1 | test1/w005_7_s4/I1 |
| 31.765 | 1.099 | tINS | FF | 2 | test1/w005_7_s4/F |
| 32.725 | 0.960 | tNET | FF | 2 | test1/n737_1_s/I0 |
| 33.708 | 0.983 | tINS | FF | 1 | test1/n737_1_s/SUM |
| 34.668 | 0.960 | tNET | FF | 1 | test1/dac1/n22_s1/I1 |
| 35.767 | 1.099 | tINS | FF | 1 | test1/dac1/n22_s1/F |
| 36.727 | 0.960 | tNET | FF | 1 | test1/dac1/n22_s0/I1 |
| 37.826 | 1.099 | tINS | FF | 1 | test1/dac1/n22_s0/F |
| 38.786 | 0.960 | tNET | FF | 1 | test1/dac1/outshr_7_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | cpuclk | |||
| 20.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 563 | cpuclk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | test1/dac1/outshr_7_s0/CLK |
| 20.326 | -0.400 | tSu | 1 | test1/dac1/outshr_7_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 21 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 18.402, 48.350%; route: 19.200, 50.446%; tC2Q: 0.458, 1.204% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |